tic4x: sign extension using shifts

[deliverable/binutils-gdb.git] / bfd / configure.ac

diff --git a/bfd/configure.ac b/bfd/configure.ac
index 39702ce1315ef0f7a2d699cf100b3b49914ca5e4..c5bfbd5d129ceb5668cf2af76e0f227cbc5c3846 100644 (file)
--- a/bfd/configure.ac
+++ b/bfd/configure.ac
@@ -1,6 +1,6 @@
 dnl Process this file with autoconf to produce a configure script.
 dnl
-dnl   Copyright (C) 2012-2019 Free Software Foundation, Inc.
+dnl   Copyright (C) 2012-2020 Free Software Foundation, Inc.
 dnl
 dnl This file is free software; you can redistribute it and/or modify
 dnl it under the terms of the GNU General Public License as published by
@@ -458,7 +458,6 @@ do
     bfin_elf32_vec)             tb="$tb elf32-bfin.lo elf32.lo $elf" ;;
     bfin_elf32_fdpic_vec)       tb="$tb elf32-bfin.lo elf32.lo $elf" ;;
     cr16_elf32_vec)             tb="$tb elf32-cr16.lo elf32.lo $elf" ;;
-    cr16c_elf32_vec)            tb="$tb elf32-cr16c.lo elf32.lo $elf" ;;
     cris_aout_vec)              tb="$tb aout-cris.lo" ;;
     cris_elf32_vec)             tb="$tb elf32-cris.lo elf32.lo $elf" ;;
     cris_elf32_us_vec)          tb="$tb elf32-cris.lo elf32.lo $elf" ;;
@@ -660,7 +659,6 @@ do
     tic6x_elf32_c6000_le_vec)   tb="$tb elf32-tic6x.lo elf32.lo $elf" ;;
     tic6x_elf32_linux_be_vec)   tb="$tb elf32-tic6x.lo elf32.lo $elf" ;;
     tic6x_elf32_linux_le_vec)   tb="$tb elf32-tic6x.lo elf32.lo $elf" ;;
-    tic80_coff_vec)             tb="$tb coff-tic80.lo $coff" ;;
     tilegx_elf32_be_vec)        tb="$tb elf32-tilegx.lo elfxx-tilegx.lo elf32.lo $elf" ; target_size=32 ;;
     tilegx_elf32_le_vec)        tb="$tb elf32-tilegx.lo elfxx-tilegx.lo elf32.lo $elf" ; target_size=32 ;;
     tilegx_elf64_be_vec)        tb="$tb elf64-tilegx.lo elfxx-tilegx.lo elf64.lo $elf" ; target_size=64 ;;
@@ -693,6 +691,7 @@ do
     xtensa_elf32_be_vec)        tb="$tb xtensa-isa.lo xtensa-modules.lo elf32-xtensa.lo elf32.lo $elf" ;;
     xtensa_elf32_le_vec)        tb="$tb xtensa-isa.lo xtensa-modules.lo elf32-xtensa.lo elf32.lo $elf" ;;
     z80_coff_vec)               tb="$tb coff-z80.lo reloc16.lo $coffgen" ;;
+    z80_elf32_vec)              tb="$tb elf32-z80.lo elf32.lo $elf" ;;
     z8k_coff_vec)               tb="$tb coff-z8k.lo reloc16.lo $coff" ;;
 
     # These appear out of order in targets.c