Add support for the Infineon XC16X.

[deliverable/binutils-gdb.git] / bfd / configure.in

diff --git a/bfd/configure.in b/bfd/configure.in
index be917485a5d2ea128a5da8fcd94ec7ecc5d97c35..b90e1fa760ecaaaa1c2f1788364fc772ab3ed1e5 100644 (file)
--- a/bfd/configure.in
+++ b/bfd/configure.in
@@ -84,7 +84,7 @@ bfd_default_target_size=32
 AC_PROG_CC
 AC_GNU_SOURCE
 
-ALL_LINGUAS="fr tr ja es sv da zh_CN ro rw"
+ALL_LINGUAS="fr tr ja es sv da zh_CN ro rw vi"
 CY_GNU_GETTEXT
 
 # Permit host specific settings.
@@ -560,7 +560,6 @@ do
     # This list is alphabetized to make it easy to compare
     # with the two vector lists in targets.c.  For the same reason,
     # use one entry per line, even though this leads to long lines.
-    a29kcoff_big_vec)          tb="$tb coff-a29k.lo cofflink.lo" ;;
     a_out_adobe_vec)           tb="$tb aout-adobe.lo aout32.lo" ;;
     aix5coff64_vec)            tb="$tb coff64-rs6000.lo xcofflink.lo aix5ppc-core.lo"; target_size=64 ;;
     aout0_big_vec)             tb="$tb aout0.lo aout32.lo" ;;
@@ -584,6 +583,7 @@ do
     bfd_efi_app_ia64_vec)      tb="$tb efi-app-ia64.lo pepigen.lo cofflink.lo"; target_size=64 ;;
     bfd_elf32_am33lin_vec)     tb="$tb elf32-am33lin.lo elf32.lo $elf" ;;
     bfd_elf32_avr_vec)         tb="$tb elf32-avr.lo elf32.lo $elf" ;;
+    bfd_elf32_bfin_vec)                tb="$tb elf32-bfin.lo elf32.lo $elf" ;;
     bfd_elf32_big_generic_vec)         tb="$tb elf32-gen.lo elf32.lo $elf" ;;
     bfd_elf32_bigarc_vec)      tb="$tb elf32-arc.lo elf32.lo $elf" ;;
     bfd_elf32_bigarm_vec)      tb="$tb elf32-arm.lo elf32.lo $elf" ;;
@@ -624,6 +624,7 @@ do
                                 tb="$tb elf32-arm.lo elf32.lo $elf" ;;
     bfd_elf32_littlearm_vec)   tb="$tb elf32-arm.lo elf32.lo $elf" ;;
     bfd_elf32_littlemips_vec)  tb="$tb elf32-mips.lo elfxx-mips.lo elf32.lo $elf ecofflink.lo" ;;
+    bfd_elf32_m32c_vec)         tb="$tb elf32-m32c.lo elf32.lo $elf" ;;
     bfd_elf32_m32r_vec)                tb="$tb elf32-m32r.lo elf32.lo $elf" ;;
     bfd_elf32_m32rle_vec)       tb="$tb elf32-m32r.lo elf32.lo $elf" ;;
     bfd_elf32_m32rlin_vec)      tb="$tb elf32-m32r.lo elf32.lo $elf" ;;
@@ -636,6 +637,7 @@ do
     bfd_elf32_mcore_little_vec)        tb="$tb elf32-mcore.lo elf32.lo $elf" ;;
     bfd_elf32_mn10200_vec)     tb="$tb elf-m10200.lo elf32.lo $elf" ;;
     bfd_elf32_mn10300_vec)     tb="$tb elf-m10300.lo elf32.lo $elf" ;;
+    bfd_elf32_mt_vec)           tb="$tb elf32-mt.lo elf32.lo $elf" ;;
     bfd_elf32_msp430_vec)      tb="$tb elf32-msp430.lo elf32.lo $elf" ;;
     bfd_elf32_nbigmips_vec)    tb="$tb elfn32-mips.lo elfxx-mips.lo elf32.lo $elf ecofflink.lo"; target_size=64 ;;
     bfd_elf32_nlittlemips_vec) tb="$tb elfn32-mips.lo elfxx-mips.lo elf32.lo $elf ecofflink.lo"; target_size=64 ;;
@@ -645,8 +647,9 @@ do
     bfd_elf32_or32_big_vec)    tb="$tb elf32-or32.lo elf32.lo $elf" ;;
     bfd_elf32_pj_vec)           tb="$tb elf32-pj.lo elf32.lo $elf";;
     bfd_elf32_pjl_vec)          tb="$tb elf32-pj.lo elf32.lo $elf";;
-    bfd_elf32_powerpc_vec)     tb="$tb elf32-ppc.lo elf32.lo $elf" ;;
-    bfd_elf32_powerpcle_vec)   tb="$tb elf32-ppc.lo elf32.lo $elf" ;;
+    bfd_elf32_powerpc_vec)     tb="$tb elf32-ppc.lo elf-vxworks.lo elf32.lo $elf" ;;
+    bfd_elf32_powerpcle_vec)   tb="$tb elf32-ppc.lo elf-vxworks.lo elf32.lo $elf" ;;
+    bfd_elf32_powerpc_vxworks_vec) tb="$tb elf32-ppc.lo elf-vxworks.lo elf32.lo $elf" ;;
     bfd_elf32_s390_vec)                tb="$tb elf32-s390.lo elf32.lo $elf" ;;
     # FIXME: We include cofflink.lo not because it's needed for
     # bfd_elf32_sh64[l]_vec, but because we include bfd_elf32_sh[l]_vec
@@ -671,6 +674,7 @@ do
     bfd_elf32_v850_vec)                tb="$tb elf32-v850.lo elf32.lo $elf" ;;
     bfd_elf32_vax_vec)         tb="$tb elf32-vax.lo elf32.lo $elf" ;;
     bfd_elf32_xstormy16_vec)   tb="$tb elf32-xstormy16.lo elf32.lo $elf" ;;
+    bfd_elf32_xc16x_vec)               tb="$tb elf32-xc16x.lo elf32.lo $elf" ;;
     bfd_elf32_xtensa_le_vec)   tb="$tb xtensa-isa.lo xtensa-modules.lo elf32-xtensa.lo elf32.lo $elf" ;;
     bfd_elf32_xtensa_be_vec)   tb="$tb xtensa-isa.lo xtensa-modules.lo elf32-xtensa.lo elf32.lo $elf" ;;
     bfd_elf64_alpha_freebsd_vec) tb="$tb elf64-alpha.lo elf64.lo $elf"; target_size=64 ;;
@@ -739,8 +743,6 @@ do
     m68kcoff_vec)              tb="$tb coff-m68k.lo cofflink.lo" ;;
     m68kcoffun_vec)            tb="$tb coff-u68k.lo coff-m68k.lo cofflink.lo" ;;
     m68klinux_vec)             tb="$tb m68klinux.lo aout32.lo" ;;
-    m68klynx_aout_vec)         tb="$tb m68klynx.lo lynx-core.lo aout32.lo" ;;
-    m68klynx_coff_vec)         tb="$tb cf-m68klynx.lo coff-m68k.lo cofflink.lo lynx-core.lo" ;;
     m68knetbsd_vec)            tb="$tb m68knetbsd.lo aout32.lo" ;;
     m68ksysvcoff_vec)          tb="$tb coff-svm68k.lo cofflink.lo" ;;
     m88kbcs_vec)               tb="$tb coff-m88k.lo" ;;
@@ -810,7 +812,8 @@ do
     vms_vax_vec)               tb="$tb vms.lo vms-hdr.lo vms-gsd.lo vms-tir.lo vms-misc.lo" ;;
     w65_vec)                   tb="$tb coff-w65.lo reloc16.lo" ;;
     we32kcoff_vec)             tb="$tb coff-we32k.lo" ;;
-    z8kcoff_vec)               tb="$tb coff-z8k.lo reloc16.lo" ;;
+    z80coff_vec)               tb="$tb coff-z80.lo reloc16.lo" ;;
+    z8kcoff_vec)               tb="$tb coff-z8k.lo reloc16.lo cofflink.lo" ;;
 
     # These appear out of order in targets.c
     srec_vec)                  tb="$tb srec.lo" ;;
@@ -919,7 +922,7 @@ AC_SUBST(bfd_default_target_size)
 # fseeko, long.  This assumes that sizeof off_t is .ge. sizeof long.
 # Hopefully a reasonable assumption since fseeko et.al. should be
 # upward compatible.
-AC_CHECK_FUNCS(ftello ftello64 fseeko fseeko64)
+AC_CHECK_FUNCS(ftello ftello64 fseeko fseeko64 fopen64)
 if test x"$ac_cv_func_ftello" = xyes -a x"$ac_cv_func_fseeko" = xyes; then
     AC_CHECK_SIZEOF(off_t)
 fi