Check the correct arch_info object's mach field: all PowerPC machines are

[deliverable/binutils-gdb.git] / bfd / cpu-ia64-opc.c

diff --git a/bfd/cpu-ia64-opc.c b/bfd/cpu-ia64-opc.c
index 84774d228d6256b3c59a09fbc24283e9cf04e0ec..3cafb9f14d9f090ba1b54751c84fb53fbf705335 100644 (file)
--- a/bfd/cpu-ia64-opc.c
+++ b/bfd/cpu-ia64-opc.c
@@ -1,4 +1,4 @@
-/* Copyright (C) 1998, 1999  Free Software Foundation, Inc.
+/* Copyright 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
    Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
 
 This file is part of BFD, the Binary File Descriptor library.
@@ -19,7 +19,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
 
 /* Logically, this code should be part of libopcode but since some of
    the operand insertion/extraction functions help bfd to implement
-   relocations, this code is included as part of elf64-ia64.c.  This
+   relocations, this code is included as part of cpu-ia64.c.  This
    avoids circular dependencies between libopcode and libbfd and also
    obviates the need for applications to link in libopcode when all
    they really want is libbfd.
@@ -161,8 +161,8 @@ static const char*
 ext_imms_scaled (const struct ia64_operand *self, ia64_insn code,
                 ia64_insn *valuep, int scale)
 {
-  int i, bits = 0, total = 0, shift;
-  BFD_HOST_64_BIT val = 0;
+  int i, bits = 0, total = 0;
+  BFD_HOST_64_BIT val = 0, sign;
 
   for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
     {
@@ -172,8 +172,8 @@ ext_imms_scaled (const struct ia64_operand *self, ia64_insn code,
       total += bits;
     }
   /* sign extend: */
-  shift = 8*sizeof (val) - total;
-  val = (val << shift) >> shift;
+  sign = (BFD_HOST_64_BIT) 1 << (total - 1);
+  val = (val ^ sign) - sign;
 
   *valuep = (val << scale);
   return 0;
@@ -188,10 +188,7 @@ ins_imms (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
 static const char*
 ins_immsu4 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
 {
-  if (value == (BFD_HOST_U_64_BIT) 0x100000000)
-    value = 0;
-  else
-    value = (((BFD_HOST_64_BIT)value << 32) >> 32);
+  value = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
 
   return ins_imms_scaled (self, value, code, 0);
 }
@@ -213,10 +210,7 @@ static const char*
 ins_immsm1u4 (const struct ia64_operand *self, ia64_insn value,
              ia64_insn *code)
 {
-  if (value == (BFD_HOST_U_64_BIT) 0x100000000)
-    value = 0;
-  else
-    value = (((BFD_HOST_64_BIT)value << 32) >> 32);
+  value = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
 
   --value;
   return ins_imms_scaled (self, value, code, 0);
@@ -418,10 +412,11 @@ const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT] =
   {
     /* constants: */
     { CST, ins_const, ext_const, "NIL",                {{ 0, 0}}, 0, "<none>" },
+    { CST, ins_const, ext_const, "ar.csd",     {{ 0, 0}}, 0, "ar.csd" },
     { CST, ins_const, ext_const, "ar.ccv",     {{ 0, 0}}, 0, "ar.ccv" },
     { CST, ins_const, ext_const, "ar.pfs",     {{ 0, 0}}, 0, "ar.pfs" },
     { CST, ins_const, ext_const, "1",          {{ 0, 0}}, 0, "1" },
-    { CST, ins_const, ext_const, "8",          {{ 0, 0}}, 0, "1" },
+    { CST, ins_const, ext_const, "8",          {{ 0, 0}}, 0, "8" },
     { CST, ins_const, ext_const, "16",         {{ 0, 0}}, 0, "16" },
     { CST, ins_const, ext_const, "r0",         {{ 0, 0}}, 0, "r0" },
     { CST, ins_const, ext_const, "ip",         {{ 0, 0}}, 0, "ip" },
@@ -551,7 +546,7 @@ const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT] =
       "a 21-bit unsigned" },
     { ABS, ins_imms,  ext_imms,  0,                            /* IMM22 */
       {{ 7, 13}, { 9, 27}, { 5, 22}, { 1, 36}}, SDEC,
-      "a 22-bit integer" },
+      "a 22-bit signed integer" },
     { ABS, ins_immu,  ext_immu,  0,                            /* IMMU24 */
       {{21,  6}, { 2, 31}, { 1, 36}}, 0,
       "a 24-bit unsigned" },
@@ -586,4 +581,7 @@ const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT] =
       "a branch target" },
     { REL, ins_rsvd, ext_rsvd, 0, {{0, 0}}, 0,                  /* TGT64  */
       "a branch target" },
+
+    { ABS, ins_const, ext_const, 0, {{0, 0}}, 0,               /* LDXMOV */
+      "ldxmov target" },
   };