/* MSP430-specific support for 32-bit ELF
- Copyright (C) 2002-2015 Free Software Foundation, Inc.
+ Copyright (C) 2002-2016 Free Software Foundation, Inc.
Contributed by Dmitry Diky <diwil@mail.ru>
This file is part of BFD, the Binary File Descriptor library.
#include "elf-bfd.h"
#include "elf/msp430.h"
+static bfd_reloc_status_type
+rl78_sym_diff_handler (bfd * abfd,
+ arelent * reloc,
+ asymbol * sym ATTRIBUTE_UNUSED,
+ void * addr ATTRIBUTE_UNUSED,
+ asection * input_sec,
+ bfd * out_bfd ATTRIBUTE_UNUSED,
+ char ** error_message ATTRIBUTE_UNUSED)
+{
+ bfd_size_type octets;
+ octets = reloc->address * bfd_octets_per_byte (abfd);
+
+ /* Catch the case where bfd_install_relocation would return
+ bfd_reloc_outofrange because the SYM_DIFF reloc is being used in a very
+ small section. It does not actually matter if this happens because all
+ that SYM_DIFF does is compute a (4-byte) value. A second reloc then uses
+ this value, and it is that reloc that must fit into the section.
+
+ This happens in eg, gcc/testsuite/gcc.c-torture/compile/labels-3.c. */
+ if ((octets + bfd_get_reloc_size (reloc->howto))
+ > bfd_get_section_limit_octets (abfd, input_sec))
+ return bfd_reloc_ok;
+ return bfd_reloc_continue;
+}
+
static reloc_howto_type elf_msp430_howto_table[] =
{
HOWTO (R_MSP430_NONE, /* type */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont,/* complain_on_overflow */
- NULL, /* special handler. */
+ rl78_sym_diff_handler, /* special handler. */
"R_MSP430_SYM_DIFF", /* name */
FALSE, /* partial_inplace */
0xffffffff, /* src_mask */
0xffffffff, /* dst_mask */
- FALSE) /* pcrel_offset */
+ FALSE) /* pcrel_offset */
};
static reloc_howto_type elf_msp430x_howto_table[] =
TRUE), /* pcrel_offset */
EMPTY_HOWTO (R_MSP430_EHTYPE),
-
+
/* A 10 bit PC relative relocation. */
HOWTO (R_MSP430X_10_PCREL, /* type */
1, /* rightshift */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont,/* complain_on_overflow */
- NULL, /* special handler. */
+ rl78_sym_diff_handler, /* special handler. */
"R_MSP430X_SYM_DIFF", /* name */
FALSE, /* partial_inplace */
0xffffffff, /* src_mask */
0xffffffff, /* dst_mask */
- FALSE) /* pcrel_offset */
+ FALSE) /* pcrel_offset */
};
/* Map BFD reloc types to MSP430 ELF reloc types. */
const Elf_Internal_Rela *rel;
const Elf_Internal_Rela *rel_end;
- if (info->relocatable)
+ if (bfd_link_relocatable (info))
return TRUE;
symtab_hdr = &elf_tdata (abfd)->symtab_hdr;
if (sym_diff_section != NULL)
{
BFD_ASSERT (sym_diff_section == input_section);
-
+
if (uses_msp430x_relocs (input_bfd))
switch (howto->type)
{
default:
return bfd_reloc_dangerous;
}
-
+
sym_diff_section = NULL;
}
break;
case R_MSP430X_PCR20_EXT_ODST:
- /* [0,4]+[48,16] = ---F ---- FFFF */
+ /* [0,4]+[48,16] = ---F ---- ---- FFFF */
contents += rel->r_offset;
srel = (bfd_signed_vma) relocation;
if (is_rel_reloc)
{
bfd_vma addend;
addend = (bfd_get_16 (input_bfd, contents) & 0xf) << 16;
- addend |= bfd_get_16 (input_bfd, contents+4);
+ addend |= bfd_get_16 (input_bfd, contents + 6);
srel += addend;
-
+
}
else
srel += rel->r_addend;
break;
case R_MSP430X_ABS20_EXT_SRC:
- /* [7,4]+[32,16] = -78- FFFF */
+ /* [7,4]+[32,16] = -78- ---- FFFF */
contents += rel->r_offset;
srel = (bfd_signed_vma) relocation;
if (is_rel_reloc)
{
bfd_vma addend;
addend = (bfd_get_16 (input_bfd, contents) & 0x0780) << 9;
- addend |= bfd_get_16 (input_bfd, contents+2);
+ addend |= bfd_get_16 (input_bfd, contents + 4);
srel += addend;
}
else
break;
case R_MSP430X_PCR20_EXT_DST:
- /* [0,4]+[32,16] = ---F FFFF */
+ /* [0,4]+[32,16] = ---F ---- FFFF */
contents += rel->r_offset;
srel = (bfd_signed_vma) relocation;
if (is_rel_reloc)
{
bfd_vma addend;
addend = (bfd_get_16 (input_bfd, contents) & 0xf) << 16;
- addend |= bfd_get_16 (input_bfd, contents+2);
+ addend |= bfd_get_16 (input_bfd, contents + 4);
srel += addend;
}
else
break;
case R_MSP430X_PCR20_EXT_SRC:
- /* [7,4]+32,16] = -78- FFFF */
+ /* [7,4]+[32,16] = -78- ---- FFFF */
contents += rel->r_offset;
srel = (bfd_signed_vma) relocation;
if (is_rel_reloc)
{
bfd_vma addend;
addend = ((bfd_get_16 (input_bfd, contents) & 0x0780) << 9);
- addend |= bfd_get_16 (input_bfd, contents+2);
+ addend |= bfd_get_16 (input_bfd, contents + 4);
srel += addend;;
}
else
break;
case R_MSP430X_ABS20_EXT_DST:
+ /* [0,4]+[32,16] = ---F ---- FFFF */
contents += rel->r_offset;
srel = (bfd_signed_vma) relocation;
if (is_rel_reloc)
- srel += bfd_get_16 (input_bfd, contents) & 0xf;
+ {
+ bfd_vma addend;
+ addend = (bfd_get_16 (input_bfd, contents) & 0xf) << 16;
+ addend |= bfd_get_16 (input_bfd, contents + 4);
+ srel += addend;
+ }
else
srel += rel->r_addend;
bfd_put_16 (input_bfd, (srel & 0xffff), contents + 4);
break;
case R_MSP430X_ABS20_EXT_ODST:
- /* [0,4]+[48,16] = ---F ---- FFFF */
+ /* [0,4]+[48,16] = ---F ---- ---- FFFF */
contents += rel->r_offset;
srel = (bfd_signed_vma) relocation;
if (is_rel_reloc)
{
bfd_vma addend;
addend = (bfd_get_16 (input_bfd, contents) & 0xf) << 16;
- addend |= bfd_get_16 (input_bfd, contents+4);
+ addend |= bfd_get_16 (input_bfd, contents + 6);
srel += addend;
}
else
break;
case R_MSP430X_ABS20_ADR_SRC:
- /* [8,4]+[32,16] = -F-- FFFF */
+ /* [8,4]+[16,16] = -F-- FFFF */
contents += rel->r_offset;
srel = (bfd_signed_vma) relocation;
if (is_rel_reloc)
bfd_vma addend;
addend = ((bfd_get_16 (input_bfd, contents) & 0xf00) << 8);
- addend |= bfd_get_16 (input_bfd, contents+2);
+ addend |= bfd_get_16 (input_bfd, contents + 2);
srel += addend;
}
else
break;
case R_MSP430X_ABS20_ADR_DST:
- /* [0,4]+[32,16] = ---F FFFF */
+ /* [0,4]+[16,16] = ---F FFFF */
contents += rel->r_offset;
srel = (bfd_signed_vma) relocation;
if (is_rel_reloc)
{
bfd_vma addend;
addend = ((bfd_get_16 (input_bfd, contents) & 0xf) << 16);
- addend |= bfd_get_16 (input_bfd, contents+2);
+ addend |= bfd_get_16 (input_bfd, contents + 2);
srel += addend;
}
else
srel += rel->r_addend;
x = srel;
if (x > 0xffff)
- return bfd_reloc_overflow;
+ return bfd_reloc_overflow;
bfd_put_16 (input_bfd, srel & 0xffff, contents);
break;
srel += rel->r_addend;
bfd_put_16 (input_bfd, (srel >> 16) & 0xffff, contents);
break;
-
+
case R_MSP430X_PCR20_CALL:
- /* [0,4]+[32,16] = ---F FFFF*/
+ /* [0,4]+[16,16] = ---F FFFF*/
contents += rel->r_offset;
srel = (bfd_signed_vma) relocation;
if (is_rel_reloc)
{
bfd_vma addend;
addend = (bfd_get_16 (input_bfd, contents) & 0xf) << 16;
- addend |= bfd_get_16 (input_bfd, contents+2);
+ addend |= bfd_get_16 (input_bfd, contents + 2);
srel += addend;
}
else
x = (x & 0xfff0) | (srel & 0xf);
bfd_put_16 (input_bfd, x, contents);
break;
-
+
case R_MSP430X_PCR16:
contents += rel->r_offset;
srel = (bfd_signed_vma) relocation;
input_section->output_offset);
bfd_put_16 (input_bfd, srel & 0xffff, contents);
break;
-
+
case R_MSP430_PREL31:
contents += rel->r_offset;
srel = (bfd_signed_vma) relocation;
x = (x & 0x80000000) | ((srel >> 31) & 0x7fffffff);
bfd_put_32 (input_bfd, x, contents);
break;
-
+
default:
r = _bfd_final_link_relocate (howto, input_bfd, input_section,
contents, rel->r_offset,
}
return bfd_reloc_overflow;
}
-
+
x = bfd_get_16 (input_bfd, contents);
x = (x & 0xfc00) | (srel & 0x3ff);
bfd_put_16 (input_bfd, x, contents);
bfd_put_8 (input_bfd, srel & 0xff, contents);
break;
-
+
case R_MSP430_SYM_DIFF:
/* Cache the input section and value.
The offset is unreliable, since relaxation may
RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
rel, 1, relend, howto, 0, contents);
- if (info->relocatable)
+ if (bfd_link_relocatable (info))
continue;
r = msp430_final_link_relocate (howto, input_bfd, input_section,
case E_MSP430_MACH_MSP430X: e_set = bfd_mach_msp430x; break;
}
}
-
+
return bfd_default_set_arch_mach (abfd, bfd_arch_msp430, e_set);
}
unsigned int sidx = ELF32_R_SYM(irel->r_info);
Elf_Internal_Sym *lsym = isym + sidx;
- /* Adjust symbols referenced by .sec+0xXX */
+ /* Adjust symbols referenced by .sec+0xXX. */
if (irel->r_addend > addr && irel->r_addend < toaddr
&& sidx < symtab_hdr->sh_info
&& lsym->st_shndx == sec_shndx)
irel->r_addend -= count;
}
-
+
return TRUE;
}
for (p = abfd->sections; p != NULL; p = p->next)
msp430_elf_relax_adjust_locals (abfd,p,addr,count,sec_shndx,toaddr);
-
+
/* Adjust the local symbols defined in this section. */
symtab_hdr = & elf_tdata (abfd)->symtab_hdr;
isym = (Elf_Internal_Sym *) symtab_hdr->contents;
if (isym->st_shndx != sec_shndx)
continue;
-
+
if (isym->st_value > addr
&& (isym->st_value < toaddr
/* We also adjust a symbol at the end of the section if its name is
/* Update the section information. */
sec->size += 4;
- elf_section_data (sec)->this_hdr.contents = contents;
+ elf_section_data (sec)->this_hdr.contents = contents;
/* Adjust all the relocs. */
irel = elf_section_data (sec)->relocs;
return contents;
}
-
+
static bfd_boolean
msp430_elf_relax_section (bfd * abfd, asection * sec,
struct bfd_link_info * link_info,
/* We don't have to do anything for a relocatable link, if
this section does not have relocs, or if this is not a
code section. */
- if (link_info->relocatable
+ if (bfd_link_relocatable (link_info)
|| (sec->flags & SEC_RELOC) == 0
|| sec->reloc_count == 0 || (sec->flags & SEC_CODE) == 0)
return TRUE;
/* Get the opcode. */
opcode = bfd_get_16 (abfd, contents + irel->r_offset);
-
+
/* Compute the new opcode. We are going to convert:
J<cond> label
into:
1: */
switch (opcode & 0xfc00)
{
- case 0x3800: opcode = 0x3402; break; /* Jl -> Jge +2 */
+ case 0x3800: opcode = 0x3402; break; /* Jl -> Jge +2 */
case 0x3400: opcode = 0x3802; break; /* Jge -> Jl +2 */
case 0x2c00: opcode = 0x2802; break; /* Jhs -> Jlo +2 */
case 0x2800: opcode = 0x2c02; break; /* Jlo -> Jhs +2 */
/* Insert the new branch instruction. */
if (uses_msp430x_relocs (abfd))
{
- /* Insert an absolute branch (aka MOVA) instruction. */
+ /* Insert an absolute branch (aka MOVA) instruction. */
contents = msp430_elf_relax_add_two_words
(abfd, sec, irel->r_offset + 2, 0x0080, 0x0000);
/* Try to turn a 16bit pc-relative branch into a 10bit pc-relative
branch. */
- /* Paranoia? paranoia... */
+ /* Paranoia? paranoia... */
if (! uses_msp430x_relocs (abfd)
&& ELF32_R_TYPE (irel->r_info) == (int) R_MSP430_RL_PCREL)
{
value -= (sec->output_section->vma + sec->output_offset);
value -= irel->r_offset;
value += irel->r_addend;
-
+
/* See if the value will fit in 10 bits, note the high value is
1016 as the target will be two bytes closer if we are
able to relax. */
data_model (in_attr[OFBA_MSPABI_Tag_Data_Model].i));
result = FALSE;
}
-
+
return result;
}
return _bfd_elf_is_local_label_name (abfd, sym->name);
}
+static bfd_boolean
+uses_large_model (bfd *abfd)
+{
+ obj_attribute * attr;
+
+ if (abfd->flags & BFD_LINKER_CREATED)
+ return FALSE;
+
+ attr = elf_known_obj_attributes_proc (abfd);
+ if (attr == NULL)
+ return FALSE;
+
+ return attr[OFBA_MSPABI_Tag_Code_Model].i == 2;
+}
+
+static unsigned int
+elf32_msp430_eh_frame_address_size (bfd *abfd, asection *sec ATTRIBUTE_UNUSED)
+{
+ return uses_large_model (abfd) ? 4 : 2;
+}
+
/* This is gross. The MSP430 EABI says that (sec 11.5):
"An implementation may choose to use Rel or Rela
type relocations for other relocations."
But it also says that:
-
+
"Certain relocations are identified as Rela only. [snip]
Where Rela is specified, an implementation must honor
this requirement."
#undef elf_backend_obj_attrs_arg_type
#define elf_backend_obj_attrs_arg_type elf32_msp430_obj_attrs_arg_type
#define bfd_elf32_bfd_merge_private_bfd_data elf32_msp430_merge_private_bfd_data
+#define elf_backend_eh_frame_address_size elf32_msp430_eh_frame_address_size
#define ELF_ARCH bfd_arch_msp430
#define ELF_MACHINE_CODE EM_MSP430
#undef elf32_bed
#define elf32_bed elf32_msp430_ti_bed
-#undef ELF_OSABI
+#undef ELF_OSABI
#define ELF_OSABI ELFOSABI_NONE
static const struct bfd_elf_special_section msp430_ti_elf_special_sections[] =
{ NULL, 0, 0, 0, 0 }
};
+#undef elf_backend_special_sections
+#define elf_backend_special_sections msp430_ti_elf_special_sections
+
#include "elf32-target.h"
projects / deliverable / binutils-gdb.git / blobdiff