/* BFD support for handling relocation entries.
Copyright 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
- 2000, 2001, 2002, 2003
+ 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
Free Software Foundation, Inc.
Written by Cygnus Support.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
+ the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+ MA 02110-1301, USA. */
/*
SECTION
/* DO compile in the reloc_code name table from libbfd.h. */
#define _BFD_MAKE_TABLE_bfd_reloc_code_real
-#include "bfd.h"
#include "sysdep.h"
+#include "bfd.h"
#include "bfdlink.h"
#include "libbfd.h"
/*
.typedef struct reloc_cache_entry
.{
. {* A pointer into the canonical table of pointers. *}
-. struct symbol_cache_entry **sym_ptr_ptr;
+. struct bfd_symbol **sym_ptr_ptr;
.
. {* offset in section. *}
. bfd_size_type address;
. {* Do not complain on overflow. *}
. complain_overflow_dont,
.
-. {* Complain if the bitfield overflows, whether it is considered
-. as signed or unsigned. *}
+. {* Complain if the value overflows when considered as a signed
+. number one bit larger than the field. ie. A bitfield of N bits
+. is allowed to represent -2**n to 2**n-1. *}
. complain_overflow_bitfield,
.
-. {* Complain if the value overflows when considered as signed
+. {* Complain if the value overflows when considered as a signed
. number. *}
. complain_overflow_signed,
.
information that libbfd needs to know to tie up a back end's data.
CODE_FRAGMENT
-.struct symbol_cache_entry; {* Forward declaration. *}
+.struct bfd_symbol; {* Forward declaration. *}
.
.struct reloc_howto_struct
.{
.
. {* If this field is non null, then the supplied function is
. called rather than the normal function. This allows really
-. strange relocation methods to be accomodated (e.g., i960 callj
+. strange relocation methods to be accommodated (e.g., i960 callj
. instructions). *}
. bfd_reloc_status_type (*special_function)
-. (bfd *, arelent *, struct symbol_cache_entry *, void *, asection *,
+. (bfd *, arelent *, struct bfd_symbol *, void *, asection *,
. bfd *, char **);
.
. {* The textual name of the relocation type. *}
bfd_vma fieldmask, addrmask, signmask, ss, a;
bfd_reloc_status_type flag = bfd_reloc_ok;
- a = relocation;
-
/* Note: BITSIZE should always be <= ADDRSIZE, but in case it's not,
we'll be permissive: extra bits in the field mask will
automatically extend the address mask for purposes of the
overflow check. */
fieldmask = N_ONES (bitsize);
+ signmask = ~fieldmask;
addrmask = N_ONES (addrsize) | fieldmask;
+ a = (relocation & addrmask) >> rightshift;;
switch (how)
{
case complain_overflow_signed:
/* If any sign bits are set, all sign bits must be set. That
is, A must be a valid negative address after shifting. */
- a = (a & addrmask) >> rightshift;
signmask = ~ (fieldmask >> 1);
- ss = a & signmask;
- if (ss != 0 && ss != ((addrmask >> rightshift) & signmask))
- flag = bfd_reloc_overflow;
- break;
-
- case complain_overflow_unsigned:
- /* We have an overflow if the address does not fit in the field. */
- a = (a & addrmask) >> rightshift;
- if ((a & ~ fieldmask) != 0)
- flag = bfd_reloc_overflow;
- break;
+ /* Fall thru */
case complain_overflow_bitfield:
/* Bitfields are sometimes signed, sometimes unsigned. We
of n bits is allowed to store -2**n to 2**n-1. Thus overflow
if the value has some, but not all, bits set outside the
field. */
- a >>= rightshift;
- ss = a & ~ fieldmask;
- if (ss != 0 && ss != (((bfd_vma) -1 >> rightshift) & ~ fieldmask))
+ ss = a & signmask;
+ if (ss != 0 && ss != ((addrmask >> rightshift) & signmask))
+ flag = bfd_reloc_overflow;
+ break;
+
+ case complain_overflow_unsigned:
+ /* We have an overflow if the address does not fit in the field. */
+ if ((a & signmask) != 0)
flag = bfd_reloc_overflow;
break;
}
/* Is the address of the relocation really within the section? */
- if (reloc_entry->address > (input_section->_cooked_size
- / bfd_octets_per_byte (abfd)))
+ if (reloc_entry->address > bfd_get_section_limit (abfd, input_section))
return bfd_reloc_outofrange;
- /* Work out which section the relocation is targetted at and the
+ /* Work out which section the relocation is targeted at and the
initial relocation command value. */
/* Get symbol value. (Common symbols are special.) */
&& strcmp (abfd->xvec->name, "coff-Intel-little") != 0
&& strcmp (abfd->xvec->name, "coff-Intel-big") != 0)
{
-#if 1
/* For m68k-coff, the addend was being subtracted twice during
relocation with -r. Removing the line below this comment
fixes that problem; see PR 2953.
right
*/
relocation -= reloc_entry->addend;
-#endif
reloc_entry->addend = 0;
}
else
}
/* Is the address of the relocation really within the section? */
- if (reloc_entry->address > (input_section->_cooked_size
- / bfd_octets_per_byte (abfd)))
+ if (reloc_entry->address > bfd_get_section_limit (abfd, input_section))
return bfd_reloc_outofrange;
- /* Work out which section the relocation is targetted at and the
+ /* Work out which section the relocation is targeted at and the
initial relocation command value. */
/* Get symbol value. (Common symbols are special.) */
&& strcmp (abfd->xvec->name, "coff-Intel-little") != 0
&& strcmp (abfd->xvec->name, "coff-Intel-big") != 0)
{
-#if 1
-/* For m68k-coff, the addend was being subtracted twice during
- relocation with -r. Removing the line below this comment
- fixes that problem; see PR 2953.
+
+ /* For m68k-coff, the addend was being subtracted twice during
+ relocation with -r. Removing the line below this comment
+ fixes that problem; see PR 2953.
However, Ian wrote the following, regarding removing the line below,
which explains why it is still enabled: --djm
7) if they are different you have to figure out which version is
right. */
relocation -= reloc_entry->addend;
-#endif
- reloc_entry->addend = 0;
+ /* FIXME: There should be no target specific code here... */
+ if (strcmp (abfd->xvec->name, "coff-z8k") != 0)
+ reloc_entry->addend = 0;
}
else
{
bfd_vma relocation;
/* Sanity check the address. */
- if (address > input_section->_raw_size)
+ if (address > bfd_get_section_limit (input_bfd, input_section))
return bfd_reloc_outofrange;
/* This function assumes that we are dealing with a basic relocation
the size of an address. For bitfields, all the bits matter.
See also bfd_check_overflow. */
fieldmask = N_ONES (howto->bitsize);
+ signmask = ~fieldmask;
addrmask = N_ONES (bfd_arch_bits_per_address (input_bfd)) | fieldmask;
- a = relocation;
- b = x & howto->src_mask;
+ a = (relocation & addrmask) >> rightshift;
+ b = (x & howto->src_mask & addrmask) >> bitpos;
switch (howto->complain_on_overflow)
{
case complain_overflow_signed:
- a = (a & addrmask) >> rightshift;
-
/* If any sign bits are set, all sign bits must be set.
That is, A must be a valid negative address after
shifting. */
- signmask = ~ (fieldmask >> 1);
+ signmask = ~(fieldmask >> 1);
+ /* Fall thru */
+
+ case complain_overflow_bitfield:
+ /* Much like the signed check, but for a field one bit
+ wider. We allow a bitfield to represent numbers in the
+ range -2**n to 2**n-1, where n is the number of bits in the
+ field. Note that when bfd_vma is 32 bits, a 32-bit reloc
+ can't overflow, which is exactly what we want. */
ss = a & signmask;
if (ss != 0 && ss != ((addrmask >> rightshift) & signmask))
flag = bfd_reloc_overflow;
SRC_MASK has more bits than BITSIZE, we can get into
trouble; we would need to verify that B is in range, as
we do for A above. */
- signmask = ((~ howto->src_mask) >> 1) & howto->src_mask;
+ ss = ((~howto->src_mask) >> 1) & howto->src_mask;
+ ss >>= bitpos;
/* Set all the bits above the sign bit. */
- b = (b ^ signmask) - signmask;
-
- b = (b & addrmask) >> bitpos;
+ b = (b ^ ss) - ss;
/* Now we can do the addition. */
sum = a + b;
positive inputs. The test below looks only at the sign
bits, and it really just
SIGN (A) == SIGN (B) && SIGN (A) != SIGN (SUM)
- */
- signmask = (fieldmask >> 1) + 1;
- if (((~ (a ^ b)) & (a ^ sum)) & signmask)
- flag = bfd_reloc_overflow;
+ We mask with addrmask here to explicitly allow an address
+ wrap-around. The Linux kernel relies on it, and it is
+ the only way to write assembler code which can run when
+ loaded at a location 0x80000000 away from the location at
+ which it is linked. */
+ if (((~(a ^ b)) & (a ^ sum)) & signmask & addrmask)
+ flag = bfd_reloc_overflow;
break;
case complain_overflow_unsigned:
separate test, we can check for this by or-ing in the
operands when testing for the sum overflowing its final
field. */
- a = (a & addrmask) >> rightshift;
- b = (b & addrmask) >> bitpos;
sum = (a + b) & addrmask;
- if ((a | b | sum) & ~ fieldmask)
- flag = bfd_reloc_overflow;
-
- break;
-
- case complain_overflow_bitfield:
- /* Much like the signed check, but for a field one bit
- wider, and no trimming inputs with addrmask. We allow a
- bitfield to represent numbers in the range -2**n to
- 2**n-1, where n is the number of bits in the field.
- Note that when bfd_vma is 32 bits, a 32-bit reloc can't
- overflow, which is exactly what we want. */
- a >>= rightshift;
-
- signmask = ~ fieldmask;
- ss = a & signmask;
- if (ss != 0 && ss != (((bfd_vma) -1 >> rightshift) & signmask))
- flag = bfd_reloc_overflow;
-
- signmask = ((~ howto->src_mask) >> 1) & howto->src_mask;
- b = (b ^ signmask) - signmask;
-
- b >>= bitpos;
-
- sum = a + b;
-
- /* We mask with addrmask here to explicitly allow an address
- wrap-around. The Linux kernel relies on it, and it is
- the only way to write assembler code which can run when
- loaded at a location 0x80000000 away from the location at
- which it is linked. */
- signmask = fieldmask + 1;
- if (((~ (a ^ b)) & (a ^ sum)) & signmask & addrmask)
+ if ((a | b | sum) & signmask)
flag = bfd_reloc_overflow;
-
break;
default:
switch (size)
{
default:
- case 0:
abort ();
case 1:
bfd_put_8 (input_bfd, x, location);
return flag;
}
+/* Clear a given location using a given howto, by applying a relocation value
+ of zero and discarding any in-place addend. This is used for fixed-up
+ relocations against discarded symbols, to make ignorable debug or unwind
+ information more obvious. */
+
+void
+_bfd_clear_contents (reloc_howto_type *howto,
+ bfd *input_bfd,
+ bfd_byte *location)
+{
+ int size;
+ bfd_vma x = 0;
+
+ /* Get the value we are going to relocate. */
+ size = bfd_get_reloc_size (howto);
+ switch (size)
+ {
+ default:
+ case 0:
+ abort ();
+ case 1:
+ x = bfd_get_8 (input_bfd, location);
+ break;
+ case 2:
+ x = bfd_get_16 (input_bfd, location);
+ break;
+ case 4:
+ x = bfd_get_32 (input_bfd, location);
+ break;
+ case 8:
+#ifdef BFD64
+ x = bfd_get_64 (input_bfd, location);
+#else
+ abort ();
+#endif
+ break;
+ }
+
+ /* Zero out the unwanted bits of X. */
+ x &= ~howto->dst_mask;
+
+ /* Put the relocated value back in the object file. */
+ switch (size)
+ {
+ default:
+ case 0:
+ abort ();
+ case 1:
+ bfd_put_8 (input_bfd, x, location);
+ break;
+ case 2:
+ bfd_put_16 (input_bfd, x, location);
+ break;
+ case 4:
+ bfd_put_32 (input_bfd, x, location);
+ break;
+ case 8:
+#ifdef BFD64
+ bfd_put_64 (input_bfd, x, location);
+#else
+ abort ();
+#endif
+ break;
+ }
+}
+
/*
DOCDD
INODE
howto manager, , typedef arelent, Relocations
-SECTION
+SUBSECTION
The howto manager
When an application wants to create a relocation, but doesn't
The 24-bit relocation is used in some Intel 960 configurations.
+ENUM
+ BFD_RELOC_32_SECREL
+ENUMDOC
+ Section relative relocations. Some targets need this for DWARF2.
+
ENUM
BFD_RELOC_32_GOT_PCREL
ENUMX
ENUMDOC
SPARC TLS relocations
+ENUM
+ BFD_RELOC_SPU_IMM7
+ENUMX
+ BFD_RELOC_SPU_IMM8
+ENUMX
+ BFD_RELOC_SPU_IMM10
+ENUMX
+ BFD_RELOC_SPU_IMM10W
+ENUMX
+ BFD_RELOC_SPU_IMM16
+ENUMX
+ BFD_RELOC_SPU_IMM16W
+ENUMX
+ BFD_RELOC_SPU_IMM18
+ENUMX
+ BFD_RELOC_SPU_PCREL9a
+ENUMX
+ BFD_RELOC_SPU_PCREL9b
+ENUMX
+ BFD_RELOC_SPU_PCREL16
+ENUMX
+ BFD_RELOC_SPU_LO16
+ENUMX
+ BFD_RELOC_SPU_HI16
+ENUMX
+ BFD_RELOC_SPU_PPU32
+ENUMX
+ BFD_RELOC_SPU_PPU64
+ENUMDOC
+ SPU Relocations.
+
ENUM
BFD_RELOC_ALPHA_GPDISP_HI16
ENUMDOC
BFD_RELOC_LO16
ENUMDOC
Low 16 bits.
+
+ENUM
+ BFD_RELOC_HI16_PCREL
+ENUMDOC
+ High 16 bits of 32-bit pc-relative value
+ENUM
+ BFD_RELOC_HI16_S_PCREL
+ENUMDOC
+ High 16 bits of 32-bit pc-relative value, adjusted
+ENUM
+ BFD_RELOC_LO16_PCREL
+ENUMDOC
+ Low 16 bits of pc-relative value
+
+ENUM
+ BFD_RELOC_MIPS16_HI16
+ENUMDOC
+ MIPS16 high 16 bits of 32-bit value.
ENUM
- BFD_RELOC_PCREL_HI16_S
+ BFD_RELOC_MIPS16_HI16_S
ENUMDOC
- Like BFD_RELOC_HI16_S, but PC relative.
+ MIPS16 high 16 bits of 32-bit value but the low 16 bits will be sign
+ extended and added to form the final result. If the low 16
+ bits form a negative number, we need to add one to the high value
+ to compensate for the borrow when the low bits are added.
ENUM
- BFD_RELOC_PCREL_LO16
+ BFD_RELOC_MIPS16_LO16
ENUMDOC
- Like BFD_RELOC_LO16, but PC relative.
+ MIPS16 low 16 bits.
ENUM
BFD_RELOC_MIPS_LITERAL
BFD_RELOC_MIPS_RELGOT
ENUMX
BFD_RELOC_MIPS_JALR
+ENUMX
+ BFD_RELOC_MIPS_TLS_DTPMOD32
+ENUMX
+ BFD_RELOC_MIPS_TLS_DTPREL32
+ENUMX
+ BFD_RELOC_MIPS_TLS_DTPMOD64
+ENUMX
+ BFD_RELOC_MIPS_TLS_DTPREL64
+ENUMX
+ BFD_RELOC_MIPS_TLS_GD
+ENUMX
+ BFD_RELOC_MIPS_TLS_LDM
+ENUMX
+ BFD_RELOC_MIPS_TLS_DTPREL_HI16
+ENUMX
+ BFD_RELOC_MIPS_TLS_DTPREL_LO16
+ENUMX
+ BFD_RELOC_MIPS_TLS_GOTTPREL
+ENUMX
+ BFD_RELOC_MIPS_TLS_TPREL32
+ENUMX
+ BFD_RELOC_MIPS_TLS_TPREL64
+ENUMX
+ BFD_RELOC_MIPS_TLS_TPREL_HI16
+ENUMX
+ BFD_RELOC_MIPS_TLS_TPREL_LO16
ENUMDOC
MIPS ELF relocations.
COMMENT
+ENUM
+ BFD_RELOC_MIPS_COPY
+ENUMX
+ BFD_RELOC_MIPS_JUMP_SLOT
+ENUMDOC
+ MIPS ELF relocations (VxWorks extensions).
+COMMENT
+
ENUM
BFD_RELOC_FRV_LABEL16
ENUMX
BFD_RELOC_FRV_GPRELHI
ENUMX
BFD_RELOC_FRV_GPRELLO
+ENUMX
+ BFD_RELOC_FRV_GOT12
+ENUMX
+ BFD_RELOC_FRV_GOTHI
+ENUMX
+ BFD_RELOC_FRV_GOTLO
+ENUMX
+ BFD_RELOC_FRV_FUNCDESC
+ENUMX
+ BFD_RELOC_FRV_FUNCDESC_GOT12
+ENUMX
+ BFD_RELOC_FRV_FUNCDESC_GOTHI
+ENUMX
+ BFD_RELOC_FRV_FUNCDESC_GOTLO
+ENUMX
+ BFD_RELOC_FRV_FUNCDESC_VALUE
+ENUMX
+ BFD_RELOC_FRV_FUNCDESC_GOTOFF12
+ENUMX
+ BFD_RELOC_FRV_FUNCDESC_GOTOFFHI
+ENUMX
+ BFD_RELOC_FRV_FUNCDESC_GOTOFFLO
+ENUMX
+ BFD_RELOC_FRV_GOTOFF12
+ENUMX
+ BFD_RELOC_FRV_GOTOFFHI
+ENUMX
+ BFD_RELOC_FRV_GOTOFFLO
+ENUMX
+ BFD_RELOC_FRV_GETTLSOFF
+ENUMX
+ BFD_RELOC_FRV_TLSDESC_VALUE
+ENUMX
+ BFD_RELOC_FRV_GOTTLSDESC12
+ENUMX
+ BFD_RELOC_FRV_GOTTLSDESCHI
+ENUMX
+ BFD_RELOC_FRV_GOTTLSDESCLO
+ENUMX
+ BFD_RELOC_FRV_TLSMOFF12
+ENUMX
+ BFD_RELOC_FRV_TLSMOFFHI
+ENUMX
+ BFD_RELOC_FRV_TLSMOFFLO
+ENUMX
+ BFD_RELOC_FRV_GOTTLSOFF12
+ENUMX
+ BFD_RELOC_FRV_GOTTLSOFFHI
+ENUMX
+ BFD_RELOC_FRV_GOTTLSOFFLO
+ENUMX
+ BFD_RELOC_FRV_TLSOFF
+ENUMX
+ BFD_RELOC_FRV_TLSDESC_RELAX
+ENUMX
+ BFD_RELOC_FRV_GETTLSOFF_RELAX
+ENUMX
+ BFD_RELOC_FRV_TLSOFF_RELAX
+ENUMX
+ BFD_RELOC_FRV_TLSMOFF
ENUMDOC
Fujitsu Frv Relocations.
COMMENT
BFD_RELOC_MN10300_RELATIVE
ENUMDOC
Adjust by program base.
+ENUM
+ BFD_RELOC_MN10300_SYM_DIFF
+ENUMDOC
+ Together with another reloc targeted at the same location,
+ allows for a value that is the difference of two symbols
+ in the same section.
+ENUM
+ BFD_RELOC_MN10300_ALIGN
+ENUMDOC
+ The addend of this reloc is an alignment power that must
+ be honoured at the offset's location, regardless of linker
+ relaxation.
COMMENT
ENUM
BFD_RELOC_386_TLS_DTPOFF32
ENUMX
BFD_RELOC_386_TLS_TPOFF32
+ENUMX
+ BFD_RELOC_386_TLS_GOTDESC
+ENUMX
+ BFD_RELOC_386_TLS_DESC_CALL
+ENUMX
+ BFD_RELOC_386_TLS_DESC
ENUMDOC
i386/elf relocations
BFD_RELOC_X86_64_GOTTPOFF
ENUMX
BFD_RELOC_X86_64_TPOFF32
+ENUMX
+ BFD_RELOC_X86_64_GOTOFF64
+ENUMX
+ BFD_RELOC_X86_64_GOTPC32
+ENUMX
+ BFD_RELOC_X86_64_GOT64
+ENUMX
+ BFD_RELOC_X86_64_GOTPCREL64
+ENUMX
+ BFD_RELOC_X86_64_GOTPC64
+ENUMX
+ BFD_RELOC_X86_64_GOTPLT64
+ENUMX
+ BFD_RELOC_X86_64_PLTOFF64
+ENUMX
+ BFD_RELOC_X86_64_GOTPC32_TLSDESC
+ENUMX
+ BFD_RELOC_X86_64_TLSDESC_CALL
+ENUMX
+ BFD_RELOC_X86_64_TLSDESC
ENUMDOC
x86-64/elf relocations
ENUM
BFD_RELOC_CTOR
ENUMDOC
- The type of reloc used to build a contructor table - at the moment
+ The type of reloc used to build a constructor table - at the moment
probably a 32 bit wide absolute relocation, but the target can choose.
It generally does map to one of the other relocation types.
not stored in the instruction. The 2nd lowest bit comes from a 1 bit
field in the instruction.
ENUM
- BFD_RELOC_ARM_IMMEDIATE
+ BFD_RELOC_ARM_PCREL_CALL
+ENUMDOC
+ ARM 26-bit pc-relative branch for an unconditional BL or BLX instruction.
+ENUM
+ BFD_RELOC_ARM_PCREL_JUMP
+ENUMDOC
+ ARM 26-bit pc-relative branch for B or conditional BL instruction.
+
+ENUM
+ BFD_RELOC_THUMB_PCREL_BRANCH7
ENUMX
- BFD_RELOC_ARM_ADRL_IMMEDIATE
+ BFD_RELOC_THUMB_PCREL_BRANCH9
ENUMX
- BFD_RELOC_ARM_OFFSET_IMM
+ BFD_RELOC_THUMB_PCREL_BRANCH12
ENUMX
- BFD_RELOC_ARM_SHIFT_IMM
+ BFD_RELOC_THUMB_PCREL_BRANCH20
ENUMX
- BFD_RELOC_ARM_SWI
+ BFD_RELOC_THUMB_PCREL_BRANCH23
ENUMX
- BFD_RELOC_ARM_MULTI
+ BFD_RELOC_THUMB_PCREL_BRANCH25
+ENUMDOC
+ Thumb 7-, 9-, 12-, 20-, 23-, and 25-bit pc-relative branches.
+ The lowest bit must be zero and is not stored in the instruction.
+ Note that the corresponding ELF R_ARM_THM_JUMPnn constant has an
+ "nn" one smaller in all cases. Note further that BRANCH23
+ corresponds to R_ARM_THM_CALL.
+
+ENUM
+ BFD_RELOC_ARM_OFFSET_IMM
+ENUMDOC
+ 12-bit immediate offset, used in ARM-format ldr and str instructions.
+
+ENUM
+ BFD_RELOC_ARM_THUMB_OFFSET
+ENUMDOC
+ 5-bit immediate offset, used in Thumb-format ldr and str instructions.
+
+ENUM
+ BFD_RELOC_ARM_TARGET1
+ENUMDOC
+ Pc-relative or absolute relocation depending on target. Used for
+ entries in .init_array sections.
+ENUM
+ BFD_RELOC_ARM_ROSEGREL32
+ENUMDOC
+ Read-only segment base relative address.
+ENUM
+ BFD_RELOC_ARM_SBREL32
+ENUMDOC
+ Data segment base relative address.
+ENUM
+ BFD_RELOC_ARM_TARGET2
+ENUMDOC
+ This reloc is used for references to RTTI data from exception handling
+ tables. The actual definition depends on the target. It may be a
+ pc-relative or some form of GOT-indirect relocation.
+ENUM
+ BFD_RELOC_ARM_PREL31
+ENUMDOC
+ 31-bit PC relative address.
+ENUM
+ BFD_RELOC_ARM_MOVW
ENUMX
- BFD_RELOC_ARM_CP_OFF_IMM
+ BFD_RELOC_ARM_MOVT
ENUMX
- BFD_RELOC_ARM_CP_OFF_IMM_S2
+ BFD_RELOC_ARM_MOVW_PCREL
ENUMX
- BFD_RELOC_ARM_ADR_IMM
+ BFD_RELOC_ARM_MOVT_PCREL
ENUMX
- BFD_RELOC_ARM_LDR_IMM
+ BFD_RELOC_ARM_THUMB_MOVW
ENUMX
- BFD_RELOC_ARM_LITERAL
+ BFD_RELOC_ARM_THUMB_MOVT
ENUMX
- BFD_RELOC_ARM_IN_POOL
+ BFD_RELOC_ARM_THUMB_MOVW_PCREL
ENUMX
- BFD_RELOC_ARM_OFFSET_IMM8
+ BFD_RELOC_ARM_THUMB_MOVT_PCREL
+ENUMDOC
+ Low and High halfword relocations for MOVW and MOVT instructions.
+
+ENUM
+ BFD_RELOC_ARM_JUMP_SLOT
ENUMX
- BFD_RELOC_ARM_HWLITERAL
+ BFD_RELOC_ARM_GLOB_DAT
ENUMX
- BFD_RELOC_ARM_THUMB_ADD
+ BFD_RELOC_ARM_GOT32
ENUMX
- BFD_RELOC_ARM_THUMB_IMM
+ BFD_RELOC_ARM_PLT32
ENUMX
- BFD_RELOC_ARM_THUMB_SHIFT
+ BFD_RELOC_ARM_RELATIVE
ENUMX
- BFD_RELOC_ARM_THUMB_OFFSET
+ BFD_RELOC_ARM_GOTOFF
ENUMX
- BFD_RELOC_ARM_GOT12
+ BFD_RELOC_ARM_GOTPC
+ENUMDOC
+ Relocations for setting up GOTs and PLTs for shared libraries.
+
+ENUM
+ BFD_RELOC_ARM_TLS_GD32
ENUMX
- BFD_RELOC_ARM_GOT32
+ BFD_RELOC_ARM_TLS_LDO32
ENUMX
- BFD_RELOC_ARM_JUMP_SLOT
+ BFD_RELOC_ARM_TLS_LDM32
ENUMX
- BFD_RELOC_ARM_COPY
+ BFD_RELOC_ARM_TLS_DTPOFF32
ENUMX
- BFD_RELOC_ARM_GLOB_DAT
+ BFD_RELOC_ARM_TLS_DTPMOD32
ENUMX
- BFD_RELOC_ARM_PLT32
+ BFD_RELOC_ARM_TLS_TPOFF32
ENUMX
- BFD_RELOC_ARM_RELATIVE
+ BFD_RELOC_ARM_TLS_IE32
ENUMX
- BFD_RELOC_ARM_GOTOFF
+ BFD_RELOC_ARM_TLS_LE32
+ENUMDOC
+ ARM thread-local storage relocations.
+
+ENUM
+ BFD_RELOC_ARM_ALU_PC_G0_NC
ENUMX
- BFD_RELOC_ARM_GOTPC
+ BFD_RELOC_ARM_ALU_PC_G0
+ENUMX
+ BFD_RELOC_ARM_ALU_PC_G1_NC
+ENUMX
+ BFD_RELOC_ARM_ALU_PC_G1
+ENUMX
+ BFD_RELOC_ARM_ALU_PC_G2
+ENUMX
+ BFD_RELOC_ARM_LDR_PC_G0
+ENUMX
+ BFD_RELOC_ARM_LDR_PC_G1
+ENUMX
+ BFD_RELOC_ARM_LDR_PC_G2
+ENUMX
+ BFD_RELOC_ARM_LDRS_PC_G0
+ENUMX
+ BFD_RELOC_ARM_LDRS_PC_G1
+ENUMX
+ BFD_RELOC_ARM_LDRS_PC_G2
+ENUMX
+ BFD_RELOC_ARM_LDC_PC_G0
+ENUMX
+ BFD_RELOC_ARM_LDC_PC_G1
+ENUMX
+ BFD_RELOC_ARM_LDC_PC_G2
+ENUMX
+ BFD_RELOC_ARM_ALU_SB_G0_NC
+ENUMX
+ BFD_RELOC_ARM_ALU_SB_G0
+ENUMX
+ BFD_RELOC_ARM_ALU_SB_G1_NC
+ENUMX
+ BFD_RELOC_ARM_ALU_SB_G1
+ENUMX
+ BFD_RELOC_ARM_ALU_SB_G2
+ENUMX
+ BFD_RELOC_ARM_LDR_SB_G0
+ENUMX
+ BFD_RELOC_ARM_LDR_SB_G1
+ENUMX
+ BFD_RELOC_ARM_LDR_SB_G2
+ENUMX
+ BFD_RELOC_ARM_LDRS_SB_G0
+ENUMX
+ BFD_RELOC_ARM_LDRS_SB_G1
+ENUMX
+ BFD_RELOC_ARM_LDRS_SB_G2
+ENUMX
+ BFD_RELOC_ARM_LDC_SB_G0
+ENUMX
+ BFD_RELOC_ARM_LDC_SB_G1
+ENUMX
+ BFD_RELOC_ARM_LDC_SB_G2
+ENUMDOC
+ ARM group relocations.
+
+ENUM
+ BFD_RELOC_ARM_V4BX
+ENUMDOC
+ Annotation of BX instructions.
+
+ENUM
+ BFD_RELOC_ARM_IMMEDIATE
+ENUMX
+ BFD_RELOC_ARM_ADRL_IMMEDIATE
+ENUMX
+ BFD_RELOC_ARM_T32_IMMEDIATE
+ENUMX
+ BFD_RELOC_ARM_T32_ADD_IMM
+ENUMX
+ BFD_RELOC_ARM_T32_IMM12
+ENUMX
+ BFD_RELOC_ARM_T32_ADD_PC12
+ENUMX
+ BFD_RELOC_ARM_SHIFT_IMM
+ENUMX
+ BFD_RELOC_ARM_SMC
+ENUMX
+ BFD_RELOC_ARM_SWI
+ENUMX
+ BFD_RELOC_ARM_MULTI
+ENUMX
+ BFD_RELOC_ARM_CP_OFF_IMM
+ENUMX
+ BFD_RELOC_ARM_CP_OFF_IMM_S2
+ENUMX
+ BFD_RELOC_ARM_T32_CP_OFF_IMM
+ENUMX
+ BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
+ENUMX
+ BFD_RELOC_ARM_ADR_IMM
+ENUMX
+ BFD_RELOC_ARM_LDR_IMM
+ENUMX
+ BFD_RELOC_ARM_LITERAL
+ENUMX
+ BFD_RELOC_ARM_IN_POOL
+ENUMX
+ BFD_RELOC_ARM_OFFSET_IMM8
+ENUMX
+ BFD_RELOC_ARM_T32_OFFSET_U8
+ENUMX
+ BFD_RELOC_ARM_T32_OFFSET_IMM
+ENUMX
+ BFD_RELOC_ARM_HWLITERAL
+ENUMX
+ BFD_RELOC_ARM_THUMB_ADD
+ENUMX
+ BFD_RELOC_ARM_THUMB_IMM
+ENUMX
+ BFD_RELOC_ARM_THUMB_SHIFT
ENUMDOC
These relocs are only used within the ARM assembler. They are not
(at present) written to any object files.
BFD_RELOC_SH_PCDISP8BY2
ENUMX
BFD_RELOC_SH_PCDISP12BY2
+ENUMX
+ BFD_RELOC_SH_IMM3
+ENUMX
+ BFD_RELOC_SH_IMM3U
+ENUMX
+ BFD_RELOC_SH_DISP12
+ENUMX
+ BFD_RELOC_SH_DISP12BY2
+ENUMX
+ BFD_RELOC_SH_DISP12BY4
+ENUMX
+ BFD_RELOC_SH_DISP12BY8
+ENUMX
+ BFD_RELOC_SH_DISP20
+ENUMX
+ BFD_RELOC_SH_DISP20BY8
ENUMX
BFD_RELOC_SH_IMM4
ENUMX
ENUMDOC
Renesas / SuperH SH relocs. Not all of these appear in object files.
-ENUM
- BFD_RELOC_THUMB_PCREL_BRANCH9
-ENUMX
- BFD_RELOC_THUMB_PCREL_BRANCH12
-ENUMX
- BFD_RELOC_THUMB_PCREL_BRANCH23
-ENUMDOC
- Thumb 23-, 12- and 9-bit pc-relative branches. The lowest bit must
- be zero and is not stored in the instruction.
-
ENUM
BFD_RELOC_ARC_B22_PCREL
ENUMDOC
stored in the instruction. The high 24 bits are installed in bits 23
through 0.
+ENUM
+ BFD_RELOC_BFIN_16_IMM
+ENUMDOC
+ ADI Blackfin 16 bit immediate absolute reloc.
+ENUM
+ BFD_RELOC_BFIN_16_HIGH
+ENUMDOC
+ ADI Blackfin 16 bit immediate absolute reloc higher 16 bits.
+ENUM
+ BFD_RELOC_BFIN_4_PCREL
+ENUMDOC
+ ADI Blackfin 'a' part of LSETUP.
+ENUM
+ BFD_RELOC_BFIN_5_PCREL
+ENUMDOC
+ ADI Blackfin.
+ENUM
+ BFD_RELOC_BFIN_16_LOW
+ENUMDOC
+ ADI Blackfin 16 bit immediate absolute reloc lower 16 bits.
+ENUM
+ BFD_RELOC_BFIN_10_PCREL
+ENUMDOC
+ ADI Blackfin.
+ENUM
+ BFD_RELOC_BFIN_11_PCREL
+ENUMDOC
+ ADI Blackfin 'b' part of LSETUP.
+ENUM
+ BFD_RELOC_BFIN_12_PCREL_JUMP
+ENUMDOC
+ ADI Blackfin.
+ENUM
+ BFD_RELOC_BFIN_12_PCREL_JUMP_S
+ENUMDOC
+ ADI Blackfin Short jump, pcrel.
+ENUM
+ BFD_RELOC_BFIN_24_PCREL_CALL_X
+ENUMDOC
+ ADI Blackfin Call.x not implemented.
+ENUM
+ BFD_RELOC_BFIN_24_PCREL_JUMP_L
+ENUMDOC
+ ADI Blackfin Long Jump pcrel.
+ENUM
+ BFD_RELOC_BFIN_GOT17M4
+ENUMX
+ BFD_RELOC_BFIN_GOTHI
+ENUMX
+ BFD_RELOC_BFIN_GOTLO
+ENUMX
+ BFD_RELOC_BFIN_FUNCDESC
+ENUMX
+ BFD_RELOC_BFIN_FUNCDESC_GOT17M4
+ENUMX
+ BFD_RELOC_BFIN_FUNCDESC_GOTHI
+ENUMX
+ BFD_RELOC_BFIN_FUNCDESC_GOTLO
+ENUMX
+ BFD_RELOC_BFIN_FUNCDESC_VALUE
+ENUMX
+ BFD_RELOC_BFIN_FUNCDESC_GOTOFF17M4
+ENUMX
+ BFD_RELOC_BFIN_FUNCDESC_GOTOFFHI
+ENUMX
+ BFD_RELOC_BFIN_FUNCDESC_GOTOFFLO
+ENUMX
+ BFD_RELOC_BFIN_GOTOFF17M4
+ENUMX
+ BFD_RELOC_BFIN_GOTOFFHI
+ENUMX
+ BFD_RELOC_BFIN_GOTOFFLO
+ENUMDOC
+ ADI Blackfin FD-PIC relocations.
+ENUM
+ BFD_RELOC_BFIN_GOT
+ENUMDOC
+ ADI Blackfin GOT relocation.
+ENUM
+ BFD_RELOC_BFIN_PLTPC
+ENUMDOC
+ ADI Blackfin PLTPC relocation.
+ENUM
+ BFD_ARELOC_BFIN_PUSH
+ENUMDOC
+ ADI Blackfin arithmetic relocation.
+ENUM
+ BFD_ARELOC_BFIN_CONST
+ENUMDOC
+ ADI Blackfin arithmetic relocation.
+ENUM
+ BFD_ARELOC_BFIN_ADD
+ENUMDOC
+ ADI Blackfin arithmetic relocation.
+ENUM
+ BFD_ARELOC_BFIN_SUB
+ENUMDOC
+ ADI Blackfin arithmetic relocation.
+ENUM
+ BFD_ARELOC_BFIN_MULT
+ENUMDOC
+ ADI Blackfin arithmetic relocation.
+ENUM
+ BFD_ARELOC_BFIN_DIV
+ENUMDOC
+ ADI Blackfin arithmetic relocation.
+ENUM
+ BFD_ARELOC_BFIN_MOD
+ENUMDOC
+ ADI Blackfin arithmetic relocation.
+ENUM
+ BFD_ARELOC_BFIN_LSHIFT
+ENUMDOC
+ ADI Blackfin arithmetic relocation.
+ENUM
+ BFD_ARELOC_BFIN_RSHIFT
+ENUMDOC
+ ADI Blackfin arithmetic relocation.
+ENUM
+ BFD_ARELOC_BFIN_AND
+ENUMDOC
+ ADI Blackfin arithmetic relocation.
+ENUM
+ BFD_ARELOC_BFIN_OR
+ENUMDOC
+ ADI Blackfin arithmetic relocation.
+ENUM
+ BFD_ARELOC_BFIN_XOR
+ENUMDOC
+ ADI Blackfin arithmetic relocation.
+ENUM
+ BFD_ARELOC_BFIN_LAND
+ENUMDOC
+ ADI Blackfin arithmetic relocation.
+ENUM
+ BFD_ARELOC_BFIN_LOR
+ENUMDOC
+ ADI Blackfin arithmetic relocation.
+ENUM
+ BFD_ARELOC_BFIN_LEN
+ENUMDOC
+ ADI Blackfin arithmetic relocation.
+ENUM
+ BFD_ARELOC_BFIN_NEG
+ENUMDOC
+ ADI Blackfin arithmetic relocation.
+ENUM
+ BFD_ARELOC_BFIN_COMP
+ENUMDOC
+ ADI Blackfin arithmetic relocation.
+ENUM
+ BFD_ARELOC_BFIN_PAGE
+ENUMDOC
+ ADI Blackfin arithmetic relocation.
+ENUM
+ BFD_ARELOC_BFIN_HWPAGE
+ENUMDOC
+ ADI Blackfin arithmetic relocation.
+ENUM
+ BFD_ARELOC_BFIN_ADDR
+ENUMDOC
+ ADI Blackfin arithmetic relocation.
+
ENUM
BFD_RELOC_D10V_10_PCREL_R
ENUMDOC
ENUMDOC
DLX relocs
+ENUM
+ BFD_RELOC_M32C_HI8
+ENUMX
+ BFD_RELOC_M32C_RL_JUMP
+ENUMX
+ BFD_RELOC_M32C_RL_1ADDR
+ENUMX
+ BFD_RELOC_M32C_RL_2ADDR
+ENUMDOC
+ Renesas M16C/M32C Relocations.
+
ENUM
BFD_RELOC_M32R_24
ENUMDOC
ENUMDOC
This is a 16-bit reloc containing the small data area offset for use in
add3, load, and store instructions.
+ENUM
+ BFD_RELOC_M32R_GOT24
+ENUMX
+ BFD_RELOC_M32R_26_PLTREL
+ENUMX
+ BFD_RELOC_M32R_COPY
+ENUMX
+ BFD_RELOC_M32R_GLOB_DAT
+ENUMX
+ BFD_RELOC_M32R_JMP_SLOT
+ENUMX
+ BFD_RELOC_M32R_RELATIVE
+ENUMX
+ BFD_RELOC_M32R_GOTOFF
+ENUMX
+ BFD_RELOC_M32R_GOTOFF_HI_ULO
+ENUMX
+ BFD_RELOC_M32R_GOTOFF_HI_SLO
+ENUMX
+ BFD_RELOC_M32R_GOTOFF_LO
+ENUMX
+ BFD_RELOC_M32R_GOTPC24
+ENUMX
+ BFD_RELOC_M32R_GOT16_HI_ULO
+ENUMX
+ BFD_RELOC_M32R_GOT16_HI_SLO
+ENUMX
+ BFD_RELOC_M32R_GOT16_LO
+ENUMX
+ BFD_RELOC_M32R_GOTPC_HI_ULO
+ENUMX
+ BFD_RELOC_M32R_GOTPC_HI_SLO
+ENUMX
+ BFD_RELOC_M32R_GOTPC_LO
+ENUMDOC
+ For PIC.
+
ENUM
BFD_RELOC_V850_9_PCREL
BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET
ENUMDOC
This is a 16 bit offset from the short data area pointer, with the
- bits placed non-contigously in the instruction.
+ bits placed non-contiguously in the instruction.
ENUM
BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET
ENUMDOC
This is a 16 bit offset from the zero data area pointer, with the
- bits placed non-contigously in the instruction.
+ bits placed non-contiguously in the instruction.
ENUM
BFD_RELOC_V850_CALLT_6_7_OFFSET
ENUMDOC
BFD_RELOC_V850_ALIGN
ENUMDOC
Used to maintain alignment whilst relaxing.
+ENUM
+ BFD_RELOC_V850_LO16_SPLIT_OFFSET
+ENUMDOC
+ This is a variation of BFD_RELOC_LO16 that can be used in v850e ld.bu
+ instructions.
ENUM
BFD_RELOC_MN10300_32_PCREL
ENUMDOC
ENUMDOC
Motorola Mcore relocations.
+ENUM
+ BFD_RELOC_MEP_8
+ENUMX
+ BFD_RELOC_MEP_16
+ENUMX
+ BFD_RELOC_MEP_32
+ENUMX
+ BFD_RELOC_MEP_PCREL8A2
+ENUMX
+ BFD_RELOC_MEP_PCREL12A2
+ENUMX
+ BFD_RELOC_MEP_PCREL17A2
+ENUMX
+ BFD_RELOC_MEP_PCREL24A2
+ENUMX
+ BFD_RELOC_MEP_PCABS24A2
+ENUMX
+ BFD_RELOC_MEP_LOW16
+ENUMX
+ BFD_RELOC_MEP_HI16U
+ENUMX
+ BFD_RELOC_MEP_HI16S
+ENUMX
+ BFD_RELOC_MEP_GPREL
+ENUMX
+ BFD_RELOC_MEP_TPREL
+ENUMX
+ BFD_RELOC_MEP_TPREL7
+ENUMX
+ BFD_RELOC_MEP_TPREL7A2
+ENUMX
+ BFD_RELOC_MEP_TPREL7A4
+ENUMX
+ BFD_RELOC_MEP_UIMM24
+ENUMX
+ BFD_RELOC_MEP_ADDR24A4
+ENUMX
+ BFD_RELOC_MEP_GNU_VTINHERIT
+ENUMX
+ BFD_RELOC_MEP_GNU_VTENTRY
+ENUMDOC
+ Toshiba Media Processor Relocations.
+COMMENT
+
ENUM
BFD_RELOC_MMIX_GETA
ENUMX
ENUMDOC
This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
of program memory address) into 8 bit immediate value of LDI insn.
+ENUM
+ BFD_RELOC_AVR_MS8_LDI
+ENUMDOC
+ This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
+ of 32 bit value) into 8 bit immediate value of LDI insn.
ENUM
BFD_RELOC_AVR_LO8_LDI_NEG
ENUMDOC
This is a 16 bit reloc for the AVR that stores negated 8 bit value
(most high 8 bit of program memory address) into 8 bit immediate value
of LDI or SUBI insn.
+ENUM
+ BFD_RELOC_AVR_MS8_LDI_NEG
+ENUMDOC
+ This is a 16 bit reloc for the AVR that stores negated 8 bit value (msb
+ of 32 bit value) into 8 bit immediate value of LDI insn.
ENUM
BFD_RELOC_AVR_LO8_LDI_PM
ENUMDOC
This is a 16 bit reloc for the AVR that stores 8 bit value (usually
command address) into 8 bit immediate value of LDI insn.
+ENUM
+ BFD_RELOC_AVR_LO8_LDI_GS
+ENUMDOC
+ This is a 16 bit reloc for the AVR that stores 8 bit value
+ (command address) into 8 bit immediate value of LDI insn. If the address
+ is beyond the 128k boundary, the linker inserts a jump stub for this reloc
+ in the lower 128k.
ENUM
BFD_RELOC_AVR_HI8_LDI_PM
ENUMDOC
This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
of command address) into 8 bit immediate value of LDI insn.
+ENUM
+ BFD_RELOC_AVR_HI8_LDI_GS
+ENUMDOC
+ This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
+ of command address) into 8 bit immediate value of LDI insn. If the address
+ is beyond the 128k boundary, the linker inserts a jump stub for this reloc
+ below 128k.
ENUM
BFD_RELOC_AVR_HH8_LDI_PM
ENUMDOC
ENUMDOC
This is a 32 bit reloc for the AVR that stores 23 bit value
into 22 bits.
+ENUM
+ BFD_RELOC_AVR_LDI
+ENUMDOC
+ This is a 16 bit reloc for the AVR that stores all needed bits
+ for absolute addressing with ldi with overflow check to linktime
+ENUM
+ BFD_RELOC_AVR_6
+ENUMDOC
+ This is a 6 bit reloc for the AVR that stores offset for ldd/std
+ instructions
+ENUM
+ BFD_RELOC_AVR_6_ADIW
+ENUMDOC
+ This is a 6 bit reloc for the AVR that stores offset for adiw/sbiw
+ instructions
ENUM
BFD_RELOC_390_12
ENUMDOC
Long displacement extension.
+ENUM
+ BFD_RELOC_SCORE_DUMMY1
+ENUMDOC
+ Score relocations
+ENUM
+ BFD_RELOC_SCORE_GPREL15
+ENUMDOC
+ Low 16 bit for load/store
+ENUM
+ BFD_RELOC_SCORE_DUMMY2
+ENUMX
+ BFD_RELOC_SCORE_JMP
+ENUMDOC
+ This is a 24-bit reloc with the right 1 bit assumed to be 0
+ENUM
+ BFD_RELOC_SCORE_BRANCH
+ENUMDOC
+ This is a 19-bit reloc with the right 1 bit assumed to be 0
+ENUM
+ BFD_RELOC_SCORE16_JMP
+ENUMDOC
+ This is a 11-bit reloc with the right 1 bit assumed to be 0
+ENUM
+ BFD_RELOC_SCORE16_BRANCH
+ENUMDOC
+ This is a 8-bit reloc with the right 1 bit assumed to be 0
+ENUM
+ BFD_RELOC_SCORE_GOT15
+ENUMX
+ BFD_RELOC_SCORE_GOT_LO16
+ENUMX
+ BFD_RELOC_SCORE_CALL15
+ENUMX
+ BFD_RELOC_SCORE_DUMMY_HI16
+ENUMDOC
+ Undocumented Score relocs
+
ENUM
BFD_RELOC_IP2K_FR9
ENUMDOC
included in the output.
VTABLE_INHERIT is a zero-space relocation used to describe to the
- linker the inheritence tree of a C++ virtual function table. The
+ linker the inheritance tree of a C++ virtual function table. The
relocation's symbol should be the parent class' vtable, and the
relocation should be located at the child vtable.
Motorola 68HC11 reloc.
This reloc marks the beginning of a jump/call instruction.
It is used for linker relaxation to correctly identify beginning
- of instruction and change some branchs to use PC-relative
+ of instruction and change some branches to use PC-relative
addressing mode.
ENUM
BFD_RELOC_M68HC11_RL_GROUP
This is a 24-bit reloc that represents the address with a 16-bit
value and a 8-bit page number. The symbol address is transformed
to follow the 16K memory bank of 68HC12 (seen as mapped in the window).
+ENUM
+ BFD_RELOC_M68HC12_5B
+ENUMDOC
+ Motorola 68HC12 reloc.
+ This is the 5 bits of a value.
+
+ENUM
+ BFD_RELOC_16C_NUM08
+ENUMX
+ BFD_RELOC_16C_NUM08_C
+ENUMX
+ BFD_RELOC_16C_NUM16
+ENUMX
+ BFD_RELOC_16C_NUM16_C
+ENUMX
+ BFD_RELOC_16C_NUM32
+ENUMX
+ BFD_RELOC_16C_NUM32_C
+ENUMX
+ BFD_RELOC_16C_DISP04
+ENUMX
+ BFD_RELOC_16C_DISP04_C
+ENUMX
+ BFD_RELOC_16C_DISP08
+ENUMX
+ BFD_RELOC_16C_DISP08_C
+ENUMX
+ BFD_RELOC_16C_DISP16
+ENUMX
+ BFD_RELOC_16C_DISP16_C
+ENUMX
+ BFD_RELOC_16C_DISP24
+ENUMX
+ BFD_RELOC_16C_DISP24_C
+ENUMX
+ BFD_RELOC_16C_DISP24a
+ENUMX
+ BFD_RELOC_16C_DISP24a_C
+ENUMX
+ BFD_RELOC_16C_REG04
+ENUMX
+ BFD_RELOC_16C_REG04_C
+ENUMX
+ BFD_RELOC_16C_REG04a
+ENUMX
+ BFD_RELOC_16C_REG04a_C
+ENUMX
+ BFD_RELOC_16C_REG14
+ENUMX
+ BFD_RELOC_16C_REG14_C
+ENUMX
+ BFD_RELOC_16C_REG16
+ENUMX
+ BFD_RELOC_16C_REG16_C
+ENUMX
+ BFD_RELOC_16C_REG20
+ENUMX
+ BFD_RELOC_16C_REG20_C
+ENUMX
+ BFD_RELOC_16C_ABS20
+ENUMX
+ BFD_RELOC_16C_ABS20_C
+ENUMX
+ BFD_RELOC_16C_ABS24
+ENUMX
+ BFD_RELOC_16C_ABS24_C
+ENUMX
+ BFD_RELOC_16C_IMM04
+ENUMX
+ BFD_RELOC_16C_IMM04_C
+ENUMX
+ BFD_RELOC_16C_IMM16
+ENUMX
+ BFD_RELOC_16C_IMM16_C
+ENUMX
+ BFD_RELOC_16C_IMM20
+ENUMX
+ BFD_RELOC_16C_IMM20_C
+ENUMX
+ BFD_RELOC_16C_IMM24
+ENUMX
+ BFD_RELOC_16C_IMM24_C
+ENUMX
+ BFD_RELOC_16C_IMM32
+ENUMX
+ BFD_RELOC_16C_IMM32_C
+ENUMDOC
+ NS CR16C Relocations.
+
+ENUM
+ BFD_RELOC_CR16_NUM8
+ENUMX
+ BFD_RELOC_CR16_NUM16
+ENUMX
+ BFD_RELOC_CR16_NUM32
+ENUMX
+ BFD_RELOC_CR16_NUM32a
+ENUMX
+ BFD_RELOC_CR16_REGREL0
+ENUMX
+ BFD_RELOC_CR16_REGREL4
+ENUMX
+ BFD_RELOC_CR16_REGREL4a
+ENUMX
+ BFD_RELOC_CR16_REGREL14
+ENUMX
+ BFD_RELOC_CR16_REGREL14a
+ENUMX
+ BFD_RELOC_CR16_REGREL16
+ENUMX
+ BFD_RELOC_CR16_REGREL20
+ENUMX
+ BFD_RELOC_CR16_REGREL20a
+ENUMX
+ BFD_RELOC_CR16_ABS20
+ENUMX
+ BFD_RELOC_CR16_ABS24
+ENUMX
+ BFD_RELOC_CR16_IMM4
+ENUMX
+ BFD_RELOC_CR16_IMM8
+ENUMX
+ BFD_RELOC_CR16_IMM16
+ENUMX
+ BFD_RELOC_CR16_IMM20
+ENUMX
+ BFD_RELOC_CR16_IMM24
+ENUMX
+ BFD_RELOC_CR16_IMM32
+ENUMX
+ BFD_RELOC_CR16_IMM32a
+ENUMX
+ BFD_RELOC_CR16_DISP4
+ENUMX
+ BFD_RELOC_CR16_DISP8
+ENUMX
+ BFD_RELOC_CR16_DISP16
+ENUMX
+ BFD_RELOC_CR16_DISP20
+ENUMX
+ BFD_RELOC_CR16_DISP24
+ENUMX
+ BFD_RELOC_CR16_DISP24a
+ENUMX
+ BFD_RELOC_CR16_SWITCH8
+ENUMX
+ BFD_RELOC_CR16_SWITCH16
+ENUMX
+ BFD_RELOC_CR16_SWITCH32
+ENUMDOC
+ NS CR16 Relocations.
+
+ENUM
+ BFD_RELOC_CRX_REL4
+ENUMX
+ BFD_RELOC_CRX_REL8
+ENUMX
+ BFD_RELOC_CRX_REL8_CMP
+ENUMX
+ BFD_RELOC_CRX_REL16
+ENUMX
+ BFD_RELOC_CRX_REL24
+ENUMX
+ BFD_RELOC_CRX_REL32
+ENUMX
+ BFD_RELOC_CRX_REGREL12
+ENUMX
+ BFD_RELOC_CRX_REGREL22
+ENUMX
+ BFD_RELOC_CRX_REGREL28
+ENUMX
+ BFD_RELOC_CRX_REGREL32
+ENUMX
+ BFD_RELOC_CRX_ABS16
+ENUMX
+ BFD_RELOC_CRX_ABS32
+ENUMX
+ BFD_RELOC_CRX_NUM8
+ENUMX
+ BFD_RELOC_CRX_NUM16
+ENUMX
+ BFD_RELOC_CRX_NUM32
+ENUMX
+ BFD_RELOC_CRX_IMM16
+ENUMX
+ BFD_RELOC_CRX_IMM32
+ENUMX
+ BFD_RELOC_CRX_SWITCH8
+ENUMX
+ BFD_RELOC_CRX_SWITCH16
+ENUMX
+ BFD_RELOC_CRX_SWITCH32
+ENUMDOC
+ NS CRX Relocations.
ENUM
BFD_RELOC_CRIS_BDISP8
BFD_RELOC_CRIS_SIGNED_6
ENUMX
BFD_RELOC_CRIS_UNSIGNED_6
+ENUMX
+ BFD_RELOC_CRIS_SIGNED_8
+ENUMX
+ BFD_RELOC_CRIS_UNSIGNED_8
+ENUMX
+ BFD_RELOC_CRIS_SIGNED_16
+ENUMX
+ BFD_RELOC_CRIS_UNSIGNED_16
+ENUMX
+ BFD_RELOC_CRIS_LAPCQ_OFFSET
ENUMX
BFD_RELOC_CRIS_UNSIGNED_4
ENUMDOC
ENUMDOC
Sony Xstormy16 Relocations.
+ENUM
+ BFD_RELOC_RELC
+ENUMDOC
+ Self-describing complex relocations.
+COMMENT
+
+ENUM
+ BFD_RELOC_XC16X_PAG
+ENUMX
+ BFD_RELOC_XC16X_POF
+ENUMX
+ BFD_RELOC_XC16X_SEG
+ENUMX
+ BFD_RELOC_XC16X_SOF
+ENUMDOC
+ Infineon Relocations.
+
ENUM
BFD_RELOC_VAX_GLOB_DAT
ENUMX
BFD_RELOC_VAX_RELATIVE
ENUMDOC
Relocations used by VAX ELF.
-
+
+ENUM
+ BFD_RELOC_MT_PC16
+ENUMDOC
+ Morpho MT - 16 bit immediate relocation.
+ENUM
+ BFD_RELOC_MT_HI16
+ENUMDOC
+ Morpho MT - Hi 16 bits of an address.
+ENUM
+ BFD_RELOC_MT_LO16
+ENUMDOC
+ Morpho MT - Low 16 bits of an address.
+ENUM
+ BFD_RELOC_MT_GNU_VTINHERIT
+ENUMDOC
+ Morpho MT - Used to tell the linker which vtable entries are used.
+ENUM
+ BFD_RELOC_MT_GNU_VTENTRY
+ENUMDOC
+ Morpho MT - Used to tell the linker which vtable entries are used.
+ENUM
+ BFD_RELOC_MT_PCINSN8
+ENUMDOC
+ Morpho MT - 8 bit immediate relocation.
+
ENUM
BFD_RELOC_MSP430_10_PCREL
ENUMX
BFD_RELOC_MSP430_16_PCREL_BYTE
ENUMX
BFD_RELOC_MSP430_16_BYTE
+ENUMX
+ BFD_RELOC_MSP430_2X_PCREL
+ENUMX
+ BFD_RELOC_MSP430_RL_PCREL
ENUMDOC
msp430 specific relocation codes
ENUMDOC
Xtensa relocation used in ELF object files for symbols that may require
PLT entries. Otherwise, this is just a generic 32-bit relocation.
+ENUM
+ BFD_RELOC_XTENSA_DIFF8
+ENUMX
+ BFD_RELOC_XTENSA_DIFF16
+ENUMX
+ BFD_RELOC_XTENSA_DIFF32
+ENUMDOC
+ Xtensa relocations to mark the difference of two local symbols.
+ These are only needed to support linker relaxation and can be ignored
+ when not relaxing. The field is set to the value of the difference
+ assuming no relaxation. The relocation encodes the position of the
+ first symbol so the linker can determine whether to adjust the field
+ value.
+ENUM
+ BFD_RELOC_XTENSA_SLOT0_OP
+ENUMX
+ BFD_RELOC_XTENSA_SLOT1_OP
+ENUMX
+ BFD_RELOC_XTENSA_SLOT2_OP
+ENUMX
+ BFD_RELOC_XTENSA_SLOT3_OP
+ENUMX
+ BFD_RELOC_XTENSA_SLOT4_OP
+ENUMX
+ BFD_RELOC_XTENSA_SLOT5_OP
+ENUMX
+ BFD_RELOC_XTENSA_SLOT6_OP
+ENUMX
+ BFD_RELOC_XTENSA_SLOT7_OP
+ENUMX
+ BFD_RELOC_XTENSA_SLOT8_OP
+ENUMX
+ BFD_RELOC_XTENSA_SLOT9_OP
+ENUMX
+ BFD_RELOC_XTENSA_SLOT10_OP
+ENUMX
+ BFD_RELOC_XTENSA_SLOT11_OP
+ENUMX
+ BFD_RELOC_XTENSA_SLOT12_OP
+ENUMX
+ BFD_RELOC_XTENSA_SLOT13_OP
+ENUMX
+ BFD_RELOC_XTENSA_SLOT14_OP
+ENUMDOC
+ Generic Xtensa relocations for instruction operands. Only the slot
+ number is encoded in the relocation. The relocation applies to the
+ last PC-relative immediate operand, or if there are no PC-relative
+ immediates, to the last immediate operand.
+ENUM
+ BFD_RELOC_XTENSA_SLOT0_ALT
+ENUMX
+ BFD_RELOC_XTENSA_SLOT1_ALT
+ENUMX
+ BFD_RELOC_XTENSA_SLOT2_ALT
+ENUMX
+ BFD_RELOC_XTENSA_SLOT3_ALT
+ENUMX
+ BFD_RELOC_XTENSA_SLOT4_ALT
+ENUMX
+ BFD_RELOC_XTENSA_SLOT5_ALT
+ENUMX
+ BFD_RELOC_XTENSA_SLOT6_ALT
+ENUMX
+ BFD_RELOC_XTENSA_SLOT7_ALT
+ENUMX
+ BFD_RELOC_XTENSA_SLOT8_ALT
+ENUMX
+ BFD_RELOC_XTENSA_SLOT9_ALT
+ENUMX
+ BFD_RELOC_XTENSA_SLOT10_ALT
+ENUMX
+ BFD_RELOC_XTENSA_SLOT11_ALT
+ENUMX
+ BFD_RELOC_XTENSA_SLOT12_ALT
+ENUMX
+ BFD_RELOC_XTENSA_SLOT13_ALT
+ENUMX
+ BFD_RELOC_XTENSA_SLOT14_ALT
+ENUMDOC
+ Alternate Xtensa relocations. Only the slot is encoded in the
+ relocation. The meaning of these relocations is opcode-specific.
ENUM
BFD_RELOC_XTENSA_OP0
ENUMX
ENUMX
BFD_RELOC_XTENSA_OP2
ENUMDOC
- Generic Xtensa relocations. Only the operand number is encoded
- in the relocation. The details are determined by extracting the
- instruction opcode.
+ Xtensa relocations for backward compatibility. These have all been
+ replaced by BFD_RELOC_XTENSA_SLOT0_OP.
ENUM
BFD_RELOC_XTENSA_ASM_EXPAND
ENUMDOC
- Xtensa relocation to mark that the assembler expanded the
+ Xtensa relocation to mark that the assembler expanded the
instructions from an original target. The expansion size is
encoded in the reloc size.
ENUM
BFD_RELOC_XTENSA_ASM_SIMPLIFY
ENUMDOC
- Xtensa relocation to mark that the linker should simplify
- assembler-expanded instructions. This is commonly used
- internally by the linker after analysis of a
+ Xtensa relocation to mark that the linker should simplify
+ assembler-expanded instructions. This is commonly used
+ internally by the linker after analysis of a
BFD_RELOC_XTENSA_ASM_EXPAND.
+ENUM
+ BFD_RELOC_Z80_DISP8
+ENUMDOC
+ 8 bit signed offset in (ix+d) or (iy+d).
+
+ENUM
+ BFD_RELOC_Z8K_DISP7
+ENUMDOC
+ DJNZ offset.
+ENUM
+ BFD_RELOC_Z8K_CALLR
+ENUMDOC
+ CALR offset.
+ENUM
+ BFD_RELOC_Z8K_IMM4L
+ENUMDOC
+ 4 bit value.
+
ENDSENUM
BFD_RELOC_UNUSED
CODE_FRAGMENT
/*
FUNCTION
bfd_reloc_type_lookup
+ bfd_reloc_name_lookup
SYNOPSIS
reloc_howto_type *bfd_reloc_type_lookup
(bfd *abfd, bfd_reloc_code_real_type code);
+ reloc_howto_type *bfd_reloc_name_lookup
+ (bfd *abfd, const char *reloc_name);
DESCRIPTION
Return a pointer to a howto structure which, when
return BFD_SEND (abfd, reloc_type_lookup, (abfd, code));
}
+reloc_howto_type *
+bfd_reloc_name_lookup (bfd *abfd, const char *reloc_name)
+{
+ return BFD_SEND (abfd, reloc_name_lookup, (abfd, reloc_name));
+}
+
static reloc_howto_type bfd_howto_32 =
-HOWTO (0, 00, 2, 32, FALSE, 0, complain_overflow_bitfield, 0, "VRT32", FALSE, 0xffffffff, 0xffffffff, TRUE);
+HOWTO (0, 00, 2, 32, FALSE, 0, complain_overflow_dont, 0, "VRT32", FALSE, 0xffffffff, 0xffffffff, TRUE);
/*
INTERNAL_FUNCTION
DESCRIPTION
Provides default handling for relaxing for back ends which
- don't do relaxing -- i.e., does nothing except make sure that the
- final size of the section is set.
+ don't do relaxing.
*/
bfd_boolean
struct bfd_link_info *link_info ATTRIBUTE_UNUSED,
bfd_boolean *again)
{
- /* We're not relaxing the section, so just copy the size info if it's
- zero. Someone else, like bfd_merge_sections, might have set it, so
- don't overwrite a non-zero value. */
- if (section->_cooked_size == 0)
- section->_cooked_size = section->_raw_size;
*again = FALSE;
return TRUE;
}
bfd_boolean
bfd_generic_gc_sections (bfd *abfd ATTRIBUTE_UNUSED,
- struct bfd_link_info *link_info ATTRIBUTE_UNUSED)
+ struct bfd_link_info *info ATTRIBUTE_UNUSED)
{
return TRUE;
}
bfd_boolean relocatable,
asymbol **symbols)
{
- /* Get enough memory to hold the stuff. */
bfd *input_bfd = link_order->u.indirect.section->owner;
asection *input_section = link_order->u.indirect.section;
-
- long reloc_size = bfd_get_reloc_upper_bound (input_bfd, input_section);
- arelent **reloc_vector = NULL;
+ long reloc_size;
+ arelent **reloc_vector;
long reloc_count;
+ bfd_size_type sz;
+ reloc_size = bfd_get_reloc_upper_bound (input_bfd, input_section);
if (reloc_size < 0)
- goto error_return;
-
- reloc_vector = bfd_malloc (reloc_size);
- if (reloc_vector == NULL && reloc_size != 0)
- goto error_return;
+ return NULL;
/* Read in the section. */
- if (!bfd_get_section_contents (input_bfd,
- input_section,
- data,
- 0,
- input_section->_raw_size))
- goto error_return;
+ sz = input_section->rawsize ? input_section->rawsize : input_section->size;
+ if (!bfd_get_section_contents (input_bfd, input_section, data, 0, sz))
+ return NULL;
- /* Don't set input_section->_cooked_size here. The caller has set
- _cooked_size or called bfd_relax_section, which sets _cooked_size.
- Despite using this generic relocation function, some targets perform
- target-specific relaxation or string merging, which happens before
- this function is called. We do not want to clobber the _cooked_size
- they computed. */
+ if (reloc_size == 0)
+ return data;
- input_section->reloc_done = TRUE;
+ reloc_vector = bfd_malloc (reloc_size);
+ if (reloc_vector == NULL)
+ return NULL;
reloc_count = bfd_canonicalize_reloc (input_bfd,
input_section,
for (parent = reloc_vector; *parent != NULL; parent++)
{
char *error_message = NULL;
- bfd_reloc_status_type r =
- bfd_perform_relocation (input_bfd,
- *parent,
- data,
- input_section,
- relocatable ? abfd : NULL,
- &error_message);
+ asymbol *symbol;
+ bfd_reloc_status_type r;
+
+ symbol = *(*parent)->sym_ptr_ptr;
+ if (symbol->section && elf_discarded_section (symbol->section))
+ {
+ bfd_byte *p;
+ static reloc_howto_type none_howto
+ = HOWTO (0, 0, 0, 0, FALSE, 0, complain_overflow_dont, NULL,
+ "unused", FALSE, 0, 0, FALSE);
+
+ p = data + (*parent)->address * bfd_octets_per_byte (input_bfd);
+ _bfd_clear_contents ((*parent)->howto, input_bfd, p);
+ (*parent)->sym_ptr_ptr = bfd_abs_section.symbol_ptr_ptr;
+ (*parent)->addend = 0;
+ (*parent)->howto = &none_howto;
+ r = bfd_reloc_ok;
+ }
+ else
+ r = bfd_perform_relocation (input_bfd,
+ *parent,
+ data,
+ input_section,
+ relocatable ? abfd : NULL,
+ &error_message);
if (relocatable)
{
break;
case bfd_reloc_overflow:
if (!((*link_info->callbacks->reloc_overflow)
- (link_info, bfd_asymbol_name (*(*parent)->sym_ptr_ptr),
+ (link_info, NULL,
+ bfd_asymbol_name (*(*parent)->sym_ptr_ptr),
(*parent)->howto->name, (*parent)->addend,
input_bfd, input_section, (*parent)->address)))
goto error_return;
}
}
}
- if (reloc_vector != NULL)
- free (reloc_vector);
+
+ free (reloc_vector);
return data;
error_return:
- if (reloc_vector != NULL)
- free (reloc_vector);
+ free (reloc_vector);
return NULL;
}
projects / deliverable / binutils-gdb.git / blobdiff