if (sec->flags & SEC_CODE)
eisd->u.eisd.flags |= EISD__M_EXE;
- if (!(sec->flags & SEC_READONLY))
+ else if (!(sec->flags & SEC_READONLY))
+ eisd->u.eisd.flags |= EISD__M_WRT | EISD__M_CRF;
+
+ /* If relocations or fixup will be applied, make this isect writeable. */
+ if (sec->flags & SEC_RELOC)
eisd->u.eisd.flags |= EISD__M_WRT | EISD__M_CRF;
if (!(sec->flags & SEC_LOAD))
sl->has_fixups = TRUE;
VEC_APPEND_EL (sl->lp, bfd_vma,
sect->output_section->vma + sect->output_offset + offset);
+ sect->output_section->flags |= SEC_RELOC;
}
+/* Add a code address fixup at address SECT + OFFSET to SHLIB. */
+
static void
alpha_vms_add_fixup_ca (struct bfd_link_info *info, bfd *src, bfd *shlib)
{
sl->has_fixups = TRUE;
VEC_APPEND_EL (sl->ca, bfd_vma,
sect->output_section->vma + sect->output_offset + offset);
+ sect->output_section->flags |= SEC_RELOC;
}
+/* Add a quad word relocation fixup at address SECT + OFFSET to SHLIB. */
+
static void
alpha_vms_add_fixup_qr (struct bfd_link_info *info, bfd *src,
bfd *shlib, bfd_vma vec)
r = VEC_APPEND (sl->qr, struct alpha_vms_vma_ref);
r->vma = sect->output_section->vma + sect->output_offset + offset;
r->ref = vec;
+ sect->output_section->flags |= SEC_RELOC;
}
static void
unsigned int shr ATTRIBUTE_UNUSED,
bfd_vma vec ATTRIBUTE_UNUSED)
{
+ /* Not yet supported. */
abort ();
}