AArch64: Add SVE DWARF registers

[deliverable/binutils-gdb.git] / binutils / ChangeLog

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+2019-05-21  Tamar Christina  <tamar.christina@arm.com>
+
+       * dwarf.c (dwarf_regnames_aarch64): Add SVE registers.
+       * testsuite/binutils-all/aarch64/sve-dwarf-registers.d: New test.
+       * testsuite/binutils-all/aarch64/sve-dwarf-registers.s: New test.
+
+2019-05-20  Faraz Shahbazker  <fshahbazker@wavecomp.com>
+
+       PR 14798
+       * testsuite/binutils-all/readelf.ss-mips: Update reference output.
+       * testsuite/binutils-all/readelf.ss-tmips: Likewise.
+
+2019-05-20  Nick Clifton  <nickc@redhat.com>
+
+       * po/ca.po: Updated Catalan translation.
+
+2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+
+       * NEWS: Mention Armv8.1-M Mainline and MVE.
+
+2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+
+       * readelf.c (arm_attr_tag_MVE_arch): New array for Tag_MVE_arch values.
+       (arm_attr_public_tag arm_attr_public_tags): Add case for Tag_MVE_arch.
+
+2019-05-14  Jamey Hicks  <jamey.hicks@gmail.com>
+
+       PR 19921
+       * objcopy.c: Add new option --verilog-data-width.  Use it to set
+       the value of VerilogDataWidth.
+       * doc/binutils.texi: Document the new option.
+       * testsuite/binutils-all/objcopy.exp: Run tests of new option.
+       * testsuite/binutils-all/verilog-1.hex: New file.
+       * testsuite/binutils-all/verilog-2.hex: New file.
+       * testsuite/binutils-all/verilog-4.hex: New file.
+       * testsuite/binutils-all/verilog-8.hex: New file.
+       * NEWS: Mention the new feature.
+
 2019-05-10  Alan Modra  <amodra@gmail.com>
 
        * testsuite/binutils-all/objdump.exp (test_objdump_disas_limited),