+2005-11-08 Nathan Sidwell <nathan@codesourcery.com>
+
+ Add ms2
+ * ms1.cpu (ms2, ms2bf): New architecture variant, cpu, machine and
+ model.
+ (f-uu8, f-uu1, f-imm16l, f-loopo, f-cb1sel, f-cb2sel, f-cb1incr,
+ f-cb2incr, f-rc3): New fields.
+ (LOOP): New instruction.
+ (JAL-HAZARD): New hazard.
+ (imm16o, loopsize, imm16l, rc3, cb1sel, cb2sel, cb1incr, cb2incr):
+ New operands.
+ (mul, muli, dbnz, iflush): Enable for ms2
+ (jal, reti): Has JAL-HAZARD.
+ (ldctxt, ldfb, stfb): Only ms1.
+ (fbcb): Only ms1,ms1-003.
+ (wfbinc, mefbinc, wfbincr, mwfbincr, fbcbincs, mfbcbincs,
+ fbcbincrs, mfbcbincrs): Enable for ms2.
+ (loop, loopu, dfbc, dwfb, fbwfb, dfbr): New ms2 insns.
+ * ms1.opc (parse_loopsize): New.
+ (parse_imm16): hi16/lo16 relocs are applicable to IMM16L.
+ (print_pcrel): New.
+
+2005-10-28 Dave Brolley <brolley@redhat.com>
+
+ Contribute the following change:
+ 2003-09-24 Dave Brolley <brolley@redhat.com>
+
+ * frv.opc: Use CGEN_ATTR_VALUE_ENUM_TYPE in place of
+ CGEN_ATTR_VALUE_TYPE.
+ * m32c.opc (m32c_cgen_insn_supported): Use CGEN_INSN_BITSET_ATTR_VALUE.
+ Use cgen_bitset_intersect_p.
+
+2005-10-27 DJ Delorie <dj@redhat.com>
+
+ * m32c.cpu (Imm-8-s4n, Imm-12-s4n): New.
+ (arith-jnz16-imm4-dst-defn, arith-jnz32-imm4-dst-defn,
+ arith-jnz-imm4-dst-mach, arith-jnz-imm4-dst): Keep track of which
+ imm operand is needed.
+ (adjnz, sbjnz): Pass the right operands.
+ (unary-insn-defn, unary16-defn, unary32-defn, unary-insn-mach,
+ unary-insn): Add -g variants for opcodes that need to support :G.
+ (not.BW:G, push.BW:G): Call it.
+ (stzx16-imm8-imm8-dsp8sb, stzx16-imm8-imm8-dsp8fb,
+ stzx16-imm8-imm8-abs16): Fix operand typos.
+ * m32c.opc (m32c_asm_hash): Support bnCND.
+ (parse_signed4n, print_signed4n): New.
+
+2005-10-26 DJ Delorie <dj@redhat.com>
+
+ * m32c.cpu (f-dsp-8-s24, Dsp-8-s24): New.
+ (mov-dspsp-dst-defn, mov-src-dspsp-defn, mov16-dspsp-dst-defn,
+ mov16-src-dspsp-defn, mov32-dspsp-dst-defn, mov32-src-dspsp-defn):
+ dsp8[sp] is signed.
+ (mov.WL:S #imm,A0/A1): dsp24 is signed (i.e. -0x800000..0xffffff).
+ (mov.BW:S r0,r1): Fix typo r1l->r1.
+ (tst): Allow :G suffix.
+ * m32c.opc (parse_signed24): New, for -0x800000..0xffffff.
+
+2005-10-26 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
+
+ * m32r.opc (parse_hi16): Do not assume a 32-bit host word size.
+
+2005-10-25 DJ Delorie <dj@redhat.com>
+
+ * m32c.cpu (add16-bQ-sp,add16-wQ-sp): Fix to allow either width by
+ making one a macro of the other.
+
+2005-10-21 DJ Delorie <dj@redhat.com>
+
+ * m32c.cpu (lde, ste): Add dsp[a0] and [a1a] addressing.
+ (indexb, indexbd, indexbs, indexw, indexwd, indexws, indexl,
+ indexld, indexls): .w variants have `1' bit.
+ (rot32.b): QI, not SI.
+ (rot32.w): HI, not SI.
+ (xchg16): HI for .w variant.
+
+2005-10-19 Nick Clifton <nickc@redhat.com>
+
+ * m32r.opc (parse_slo16): Fix bad application of previous patch.
+
+2005-10-18 Andreas Schwab <schwab@suse.de>
+
+ * m32r.opc (parse_slo16): Better version of previous patch.
+
+2005-10-14 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
+
+ * cpu/m32r.opc (parse_slo16): Do not assume a 32-bit host word
+ size.
+
+2005-07-25 DJ Delorie <dj@redhat.com>
+
+ * m32c.opc (parse_unsigned8): Add %dsp8().
+ (parse_signed8): Add %hi8().
+ (parse_unsigned16): Add %dsp16().
+ (parse_signed16): Add %lo16() and %hi16().
+ (parse_lab_5_3): Make valuep a bfd_vma *.
+
+2005-07-18 Nick Clifton <nickc@redhat.com>
+
+ * m32c.cpu (f-16-8, f-24-8, f-32-16, f-dsp-8-u24): New opcode
+ components.
+ (f-lab32-jmp-s): Fix insertion sequence.
+ (Dsp-8-u24, Lab-5-3, Lab32-jmp-s): New operands.
+ (Dsp-40-s8): Make parameter be signed.
+ (Dsp-40-s16): Likewise.
+ (Dsp-48-s8): Likewise.
+ (Dsp-48-s16): Likewise.
+ (Imm-13-u3): Likewise. (Despite its name!)
+ (BitBase16-16-s8): Make the parameter be unsigned.
+ (BitBase16-8-u11-S): Likewise.
+ (Lab-8-8, Lab-8-16, Lab-16-8, jcnd16-5, jcnd16, jcnd32, jmp16.s,
+ jmp16.b, jmp16.w, jmp32.s, jmp32.b, jmp32.w, jsp16.w, jsr32.w): Allow
+ relaxation.
+
+ * m32c.opc: Fix formatting.
+ Use safe-ctype.h instead of ctype.h
+ Move duplicated code sequences into a macro.
+ Fix compile time warnings about signedness mismatches.
+ Remove dead code.
+ (parse_lab_5_3): New parser function.
+
+2005-07-16 Jim Blandy <jimb@redhat.com>
+
+ * m32c.opc (m32c_cgen_insn_supported): Use int, not CGEN_BITSET,
+ to represent isa sets.
+
+2005-07-15 Jim Blandy <jimb@redhat.com>
+
+ * m32c.cpu, m32c.opc: Fix copyright.
+
+2005-07-14 Jim Blandy <jimb@redhat.com>
+
+ * m32c.cpu, m32c.opc: Machine description for the Renesas M32C.
+
+2005-07-14 Alan Modra <amodra@bigpond.net.au>
+
+ * ms1.opc (print_dollarhex): Correct format string.
+
+2005-07-06 Alan Modra <amodra@bigpond.net.au>
+
+ * iq2000.cpu: Include from binutils cpu dir.
+
+2005-07-05 Nick Clifton <nickc@redhat.com>
+
+ * iq2000.opc (parse_lo16, parse_mlo16): Make value parameter
+ unsigned in order to avoid compile time warnings about sign
+ conflicts.
+
+ * ms1.opc (parse_*): Likewise.
+ (parse_imm16): Use a "void *" as it is passed both signed and
+ unsigned arguments.
+
+2005-07-01 Nick Clifton <nickc@redhat.com>
+
+ * frv.opc: Update to ISO C90 function declaration style.
+ * iq2000.opc: Likewise.
+ * m32r.opc: Likewise.
+ * sh.opc: Likewise.
+
2005-06-15 Dave Brolley <brolley@redhat.com>
Contributed by Red Hat.
media-expand-halfword-to-double-semantics, mexpdhd, cmexpdhd,
cmhtob): Use new operands.
* frv.opc (CGEN_VERBOSE_ASSEMBLER_ERRORS): Define.
- (parse_even_register): New function.
+ (parse_even_register): New function.
2003-06-03 Nick Clifton <nickc@redhat.com>
projects / deliverable / binutils-gdb.git / blobdiff