+2006-03-10 DJ Delorie <dj@redhat.com>
+
+ * m32c.cpu (mul.l): New.
+ (mulu.l): New.
+
+2006-03-03 Shrirang Khisti <shrirangk@kpitcummins.com)
+
+ * xc16x.opc (parse_hash): Return NULL if the input was parsed or
+ an error message otherwise.
+ (parse_dot, parse_pof, parse_pag, parse_sof, parse_seg): Likewise.
+ Fix up comments to correctly describe the functions.
+
+2006-02-24 DJ Delorie <dj@redhat.com>
+
+ * m32c.cpu (RL_TYPE): New attribute, with macros.
+ (Lab-8-24): Add RELAX.
+ (unary-insn-defn-g, binary-arith-imm-dst-defn,
+ binary-arith-imm4-dst-defn): Add 1ADDR attribute.
+ (binary-arith-src-dst-defn): Add 2ADDR attribute.
+ (jcnd16-5, jcnd16, jcnd32, jmp16.s, jmp16.b, jmp16.w, jmp16.a,
+ jmp32.s, jmp32.b, jmp32.w, jmp32.a, jsr16.w, jsr16.a): Add JUMP
+ attribute.
+ (jsri16, jsri32): Add 1ADDR attribute.
+ (jsr32.w, jsr32.a): Add JUMP attribute.
+
+2006-02-17 Shrirang Khisti <shrirangk@kpitcummins.com>
+ Anil Paranjape <anilp1@kpitcummins.com>
+ Shilin Shakti <shilins@kpitcummins.com>
+
+ * xc16x.cpu: New file containing complete CGEN specific XC16X CPU
+ description.
+ * xc16x.opc: New file containing supporting XC16C routines.
+
+2006-02-10 Nick Clifton <nickc@redhat.com>
+
+ * iq2000.opc (parse_hi16): Truncate shifted values to 16 bits.
+
+2006-01-06 DJ Delorie <dj@redhat.com>
+
+ * m32c.cpu (mov.w:q): Fix mode.
+ (push32.b.imm): Likewise, for the comment.
+
+2005-12-16 Nathan Sidwell <nathan@codesourcery.com>
+
+ Second part of ms1 to mt renaming.
+ * mt.cpu (define-arch, define-isa): Set name to mt.
+ (define-mach): Adjust.
+ * mt.opc (CGEN_ASM_HASH): Update.
+ (mt_asm_hash, mt_cgen_insn_supported): Renamed.
+ (parse_loopsize, parse_imm16): Adjust.
+
+2005-12-13 DJ Delorie <dj@redhat.com>
+
+ * m32c.cpu (jsri): Fix order so register names aren't treated as
+ symbols.
+ (indexb, indexbd, indexbs, indexl, indexld, indexls, indexw,
+ indexwd, indexws): Fix encodings.
+
+2005-12-12 Nathan Sidwell <nathan@codesourcery.com>
+
+ * mt.cpu: Rename from ms1.cpu.
+ * mt.opc: Rename from ms1.opc.
+
+2005-12-06 Hans-Peter Nilsson <hp@axis.com>
+
+ * cris.cpu (simplecris-common-writable-specregs)
+ (simplecris-common-readable-specregs): Split from
+ simplecris-common-specregs. All users changed.
+ (cris-implemented-writable-specregs-v0)
+ (cris-implemented-readable-specregs-v0): Similar from
+ cris-implemented-specregs-v0.
+ (cris-implemented-writable-specregs-v3)
+ (cris-implemented-readable-specregs-v3)
+ (cris-implemented-writable-specregs-v8)
+ (cris-implemented-readable-specregs-v8)
+ (cris-implemented-writable-specregs-v10)
+ (cris-implemented-readable-specregs-v10)
+ (cris-implemented-writable-specregs-v32)
+ (cris-implemented-readable-specregs-v32): Similar.
+ (bdap-32-pc, move-m-pcplus-p0, move-m-spplus-p8): New
+ insns and specializations.
+
+2005-11-08 Nathan Sidwell <nathan@codesourcery.com>
+
+ Add ms2
+ * ms1.cpu (ms2, ms2bf): New architecture variant, cpu, machine and
+ model.
+ (f-uu8, f-uu1, f-imm16l, f-loopo, f-cb1sel, f-cb2sel, f-cb1incr,
+ f-cb2incr, f-rc3): New fields.
+ (LOOP): New instruction.
+ (JAL-HAZARD): New hazard.
+ (imm16o, loopsize, imm16l, rc3, cb1sel, cb2sel, cb1incr, cb2incr):
+ New operands.
+ (mul, muli, dbnz, iflush): Enable for ms2
+ (jal, reti): Has JAL-HAZARD.
+ (ldctxt, ldfb, stfb): Only ms1.
+ (fbcb): Only ms1,ms1-003.
+ (wfbinc, mefbinc, wfbincr, mwfbincr, fbcbincs, mfbcbincs,
+ fbcbincrs, mfbcbincrs): Enable for ms2.
+ (loop, loopu, dfbc, dwfb, fbwfb, dfbr): New ms2 insns.
+ * ms1.opc (parse_loopsize): New.
+ (parse_imm16): hi16/lo16 relocs are applicable to IMM16L.
+ (print_pcrel): New.
+
2005-10-28 Dave Brolley <brolley@redhat.com>
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projects / deliverable / binutils-gdb.git / blobdiff