;; Whereas the 128-bit instructions (at the moment there is only one
;; of such instructions, lddw) have the form:
;;
-;; code:8 regs:8 offset:16 imm:32 imm:32 unused:32
+;; code:8 regs:8 offset:16 imm:32 unused:32 imm:32
;;
;; In both formats `regs' is itself composed by two fields:
;;
(set (ifield f-imm64-a) (and (ifield f-imm64) (const #xffffffff)))))
(extract (sequence ()
(set (ifield f-imm64)
- (or (sll DI (zext DI (ifield f-imm64-c)) (const 32))
- (zext DI (ifield f-imm64-a)))))))
+ (or (sll UDI (zext UDI (ifield f-imm64-c)) (const 32))
+ (zext UDI (ifield f-imm64-a)))))))
;;; Operands