; Renesas M32C CPU description. -*- Scheme -*-
;
-; Copyright 2005, 2006 Free Software Foundation, Inc.
+; Copyright 2005, 2006, 2007, 2009 Free Software Foundation, Inc.
;
; Contributed by Red Hat Inc; developed under contract from Renesas.
;
;
; This program is free software; you can redistribute it and/or modify
; it under the terms of the GNU General Public License as published by
-; the Free Software Foundation; either version 2 of the License, or
+; the Free Software Foundation; either version 3 of the License, or
; (at your option) any later version.
;
; This program is distributed in the hope that it will be useful,
;
; You should have received a copy of the GNU General Public License
; along with this program; if not, write to the Free Software
-; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+; MA 02110-1301, USA.
(include "simplify.inc")
(df f-dsp-8-u16 "16 bit unsigned" (all-isas) 8 16 UINT
((value pc) (or UHI
- (and (srl value 8) #x00ff)
- (and (sll value 8) #xff00))) ; insert
+ (and (srl value 8) #xff)
+ (sll (and value #xff) 8))) ; insert
((value pc) (or UHI
- (and UHI (srl UHI value 8) #x00ff)
- (and UHI (sll UHI value 8) #xff00))) ; extract
+ (and UHI (srl UHI value 8) #xff)
+ (sll UHI (and UHI value #xff) 8))) ; extract
)
(df f-dsp-8-s16 "8 bit signed" (all-isas) 8 16 INT
((value pc) (ext INT
(trunc HI
- (or (and (srl value 8) #x00ff)
- (and (sll value 8) #xff00))))) ; insert
+ (or (and (srl value 8) #xff)
+ (sll (and value #xff) 8))))) ; insert
((value pc) (ext INT
(trunc HI
- (or (and (srl value 8) #x00ff)
- (and (sll value 8) #xff00))))) ; extract
+ (or (and (srl value 8) #xff)
+ (sll (and value #xff) 8))))) ; extract
)
(df f-dsp-16-u16 "16 bit unsigned" (all-isas) 16 16 UINT
((value pc) (or UHI
- (and (srl value 8) #x00ff)
- (and (sll value 8) #xff00))) ; insert
+ (and (srl value 8) #xff)
+ (sll (and value #xff) 8))) ; insert
((value pc) (or UHI
- (and UHI (srl UHI value 8) #x00ff)
- (and UHI (sll UHI value 8) #xff00))) ; extract
+ (and UHI (srl UHI value 8) #xff)
+ (sll UHI (and UHI value #xff) 8))) ; extract
)
(df f-dsp-16-s16 "16 bit signed" (all-isas) 16 16 INT
((value pc) (ext INT
(trunc HI
- (or (and (srl value 8) #x00ff)
- (and (sll value 8) #xff00))))) ; insert
+ (or (and (srl value 8) #xff)
+ (sll (and value #xff) 8))))) ; insert
((value pc) (ext INT
(trunc HI
- (or (and (srl value 8) #x00ff)
- (and (sll value 8) #xff00))))) ; extract
+ (or (and (srl value 8) #xff)
+ (sll (and value #xff) 8))))) ; extract
)
(dnmf f-dsp-24-u16 "16 bit unsigned" (all-isas) UINT
(df f-dsp-32-u16 "16 bit unsigned" (all-isas) 32 16 UINT
((value pc) (or UHI
- (and (srl value 8) #x00ff)
- (and (sll value 8) #xff00))) ; insert
+ (and (srl value 8) #xff)
+ (sll (and value #xff) 8))) ; insert
((value pc) (or UHI
- (and UHI (srl UHI value 8) #x00ff)
- (and UHI (sll UHI value 8) #xff00))) ; extract
+ (and UHI (srl UHI value 8) #xff)
+ (sll UHI (and UHI value #xff) 8))) ; extract
)
(df f-dsp-32-s16 "16 bit signed" (all-isas) 32 16 INT
((value pc) (ext INT
(trunc HI
- (or (and (srl value 8) #x00ff)
- (and (sll value 8) #xff00))))) ; insert
+ (or (and (srl value 8) #xff)
+ (sll (and value #xff) 8))))) ; insert
((value pc) (ext INT
(trunc HI
- (or (and (srl value 8) #x00ff)
- (and (sll value 8) #xff00))))) ; extract
+ (or (and (srl value 8) #xff)
+ (sll (and value #xff) 8))))) ; extract
)
(df f-dsp-40-u16 "16 bit unsigned" (all-isas) 40 16 UINT
((value pc) (or UHI
- (and (srl value 8) #x00ff)
- (and (sll value 8) #xff00))) ; insert
+ (and (srl value 8) #xff)
+ (sll (and value #xff) 8))) ; insert
((value pc) (or UHI
- (and UHI (srl UHI value 8) #x00ff)
- (and UHI (sll UHI value 8) #xff00))) ; extract
+ (and UHI (srl UHI value 8) #xff)
+ (sll UHI (and UHI value #xff) 8))) ; extract
)
(df f-dsp-40-s16 "16 bit signed" (all-isas) 40 16 INT
((value pc) (ext INT
(trunc HI
- (or (and (srl value 8) #x00ff)
- (and (sll value 8) #xff00))))) ; insert
+ (or (and (srl value 8) #xff)
+ (sll (and value #xff) 8))))) ; insert
((value pc) (ext INT
(trunc HI
- (or (and (srl value 8) #x00ff)
- (and (sll value 8) #xff00))))) ; extract
+ (or (and (srl value 8) #xff)
+ (sll (and value #xff) 8))))) ; extract
)
(df f-dsp-48-u16 "16 bit unsigned" (all-isas) 48 16 UINT
((value pc) (or UHI
- (and (srl value 8) #x00ff)
- (and (sll value 8) #xff00))) ; insert
+ (and (srl value 8) #xff)
+ (sll (and value #xff) 8))) ; insert
((value pc) (or UHI
- (and UHI (srl UHI value 8) #x00ff)
- (and UHI (sll UHI value 8) #xff00))) ; extract
+ (and UHI (srl UHI value 8) #xff)
+ (sll UHI (and UHI value #xff) 8))) ; extract
)
(df f-dsp-48-s16 "16 bit signed" (all-isas) 48 16 INT
((value pc) (ext INT
(trunc HI
- (or (and (srl value 8) #x00ff)
- (and (sll value 8) #xff00))))) ; insert
+ (or (and (srl value 8) #xff)
+ (sll (and value #xff) 8))))) ; insert
((value pc) (ext INT
(trunc HI
- (or (and (srl value 8) #x00ff)
- (and (sll value 8) #xff00))))) ; extract
+ (or (and (srl value 8) #xff)
+ (sll (and value #xff) 8))))) ; extract
)
(df f-dsp-64-u16 "16 bit unsigned" (all-isas) 64 16 UINT
((value pc) (or UHI
- (and (srl value 8) #x00ff)
- (and (sll value 8) #xff00))) ; insert
+ (and (srl value 8) #xff)
+ (sll (and value #xff) 8))) ; insert
((value pc) (or UHI
- (and UHI (srl UHI value 8) #x00ff)
- (and UHI (sll UHI value 8) #xff00))) ; extract
+ (and UHI (srl UHI value 8) #xff)
+ (sll UHI (and UHI value #xff) 8))) ; extract
)
(df f-dsp-8-s24 "24 bit signed" (all-isas) 8 24 INT
- ((value pc) (or SI
- (or (srl value 16) (and value #xff00))
- (sll (ext INT (trunc QI (and value #xff))) 16)))
- ((value pc) (or SI
- (or (srl value 16) (and value #xff00))
- (sll (ext INT (trunc QI (and value #xff))) 16)))
+ ((value pc) (sub SI (xor (or SI (or (and (srl value 16) #xff)
+ (and value #xff00))
+ (sll (and value #xff) 16))
+ #x800000) #x800000))
+ ((value pc) (sub SI (xor (or SI
+ (or (and (srl value 16) #xff)
+ (and value #xff00))
+ (sll (and value #xff) 16))
+ #x800000) #x800000))
)
(df f-dsp-8-u24 "24 bit unsigned" (all-isas) 8 24 UINT
(or USI
(and (srl value 16) #x0000ff)
(and value #x00ff00))
- (and (sll value 16) #xff0000))) ; insert
+ (and (sll value 16) #xff0000))) ; insert
((value pc) (or USI
(or USI
- (and USI (srl UHI value 16) #x0000ff)
- (and USI value #x00ff00))
- (and USI (sll UHI value 16) #xff0000))) ; extract
+ (and USI (srl value 16) #x0000ff)
+ (and USI value #x00ff00))
+ (and USI (sll value 16) #xff0000))) ; extract
)
(df f-dsp-40-u20 "20 bit unsigned" (all-isas) 40 20 UINT
(or USI
(and (srl value 16) #x0000ff)
(and value #x00ff00))
- (and (sll value 16) #x0f0000))) ; insert
+ (and (sll value 16) #x0f0000))) ; insert
((value pc) (or USI
(or USI
- (and USI (srl UHI value 16) #x0000ff)
- (and USI value #x00ff00))
- (and USI (sll UHI value 16) #x0f0000))) ; extract
+ (and USI (srl value 16) #x0000ff)
+ (and USI value #x00ff00))
+ (and USI (sll value 16) #x0f0000))) ; extract
)
+
(df f-dsp-40-u24 "24 bit unsigned" (all-isas) 40 24 UINT
((value pc) (or USI
(or USI
(and (srl value 16) #x0000ff)
(and value #x00ff00))
- (and (sll value 16) #xff0000))) ; insert
+ (and (sll value 16) #xff0000))) ; insert
((value pc) (or USI
(or USI
- (and USI (srl UHI value 16) #x0000ff)
- (and USI value #x00ff00))
- (and USI (sll UHI value 16) #xff0000))) ; extract
+ (and USI (srl value 16) #x0000ff)
+ (and USI value #x00ff00))
+ (and USI (sll value 16) #xff0000))) ; extract
)
(dnmf f-dsp-40-s32 "32 bit signed" (all-isas) INT
(set (ifield f-dsp-16-s16) (sra INT (ifield f-bitbase32-16-s19-unprefixed) 3))
)
(sequence () ; extract
- (set (ifield f-bitbase32-16-s19-unprefixed) (or (sll (ifield f-dsp-16-s16) 3)
+ (set (ifield f-bitbase32-16-s19-unprefixed) (or (mul (ifield f-dsp-16-s16) 8)
(ifield f-bitno32-unprefixed)))
)
)
)
(df f-lab-8-16 "16 bit pc relative signed offset" (PCREL-ADDR SIGN-OPT all-isas) 8 16 UINT
((value pc) (or SI (sll (and (sub value (add pc 1)) #xff) 8)
- (srl (and (sub value (add pc 1)) #xffff) 8)))
- ((value pc) (add SI (or (srl (and value #xffff) 8)
- (sra (sll (and value #xff) 24) 16)) (add pc 1)))
+ (srl (and (sub value (add pc 1)) #xff00) 8)))
+ ((value pc) (add SI (sub (xor (or (srl (and value #xff00) 8)
+ (sll (and value #xff) 8))
+ #x8000)
+ #x8000)
+ (add pc 1)))
)
(df f-lab-8-24 "24 bit absolute" (all-isas ABS-ADDR) 8 24 UINT
((value pc) (or SI
)
(define-full-operand Imm-8-s4n "negated 4 bit immediate at offset 8 bits" (all-isas)
h-sint DFLT f-imm-8-s4
- ((parse "signed4n")) () ()
+ ((parse "signed4n") (print "signed4n")) () ()
)
(define-full-operand Imm-sh-8-s4 "signed 4 bit shift immediate at offset 8 bits" (all-isas)
h-shimm DFLT f-imm-8-s4
(dnop Lab-8-16 "16 bit label" (all-isas RELAX) h-iaddr f-lab-8-16)
(dnop Lab-8-24 "24 bit label" (all-isas RELAX) h-iaddr f-lab-8-24)
(dnop Lab-16-8 "8 bit label" (all-isas RELAX) h-iaddr f-lab-16-8)
-(dnop Lab-24-8 "8 bit label" (all-isas) h-iaddr f-lab-24-8)
-(dnop Lab-32-8 "8 bit label" (all-isas) h-iaddr f-lab-32-8)
-(dnop Lab-40-8 "8 bit label" (all-isas) h-iaddr f-lab-40-8)
+(dnop Lab-24-8 "8 bit label" (all-isas RELAX) h-iaddr f-lab-24-8)
+(dnop Lab-32-8 "8 bit label" (all-isas RELAX) h-iaddr f-lab-32-8)
+(dnop Lab-40-8 "8 bit label" (all-isas RELAX) h-iaddr f-lab-40-8)
;-------------------------------------------------------------
; Condition code bits
(define-pmacro (arith-jnz-imm4-dst-defn mach src dstgroup label mode wstr op encoding sem)
(dni (.sym op mach wstr - imm4 - dstgroup)
(.str op wstr " " mach "-imm4-" dstgroup "-" label "-" mode)
- ((machine mach))
+ (RL_JUMP RELAXABLE (machine mach))
(.str op wstr " #${" src "},${dst" mach "-" dstgroup "-" mode "},${" label "}")
encoding
(sem mode src (.sym dst mach - dstgroup - mode) label)
(+ opc1 opc2 (f-7-1 wbit) (.sym Imm-8- i4n) (.sym dst16-basic- mode) Lab-16-8)
sem)
(arith-jnz-imm4-dst-defn 16 (.sym Imm-8- i4n) 16-16 Lab-32-8 mode wstr op
- (+ opc1 opc2 (f-7-1 wbit) (.sym Imm-8- i4n) (.sym dst16-16-16- mode) Lab-16-8)
+ (+ opc1 opc2 (f-7-1 wbit) (.sym Imm-8- i4n) (.sym dst16-16-16- mode) Lab-32-8)
sem)
(arith-jnz-imm4-dst-defn 16 (.sym Imm-8- i4n) 16-8 Lab-24-8 mode wstr op
- (+ opc1 opc2 (f-7-1 wbit) (.sym Imm-8- i4n) (.sym dst16-16-8- mode) Lab-16-8)
+ (+ opc1 opc2 (f-7-1 wbit) (.sym Imm-8- i4n) (.sym dst16-16-8- mode) Lab-24-8)
sem)
)
)