* m32c.cpu (mov.w:q): Fix mode.

[deliverable/binutils-gdb.git] / cpu / m32c.opc

diff --git a/cpu/m32c.opc b/cpu/m32c.opc
index 19547ae694daf10a4637e2f08ee5f7cfa9ddcb90..62353267f4711ac85f90c226d9412855292af0ea 100644 (file)
--- a/cpu/m32c.opc
+++ b/cpu/m32c.opc
@@ -69,6 +69,10 @@ m32c_asm_hash (const char *mnem)
   if (mnem[0] == 's' && mnem[1] == 'c')
     return 's';
   
+  /* Don't hash bmCND  */
+  if (mnem[0] == 'b' && mnem[1] == 'm')
+    return 'b';
+  
   for (h = 0; *mnem && *mnem != ' ' && *mnem != ':'; ++mnem)
     h += *mnem;
   return h % CGEN_ASM_HASH_SIZE;
@@ -217,6 +221,31 @@ parse_signed4 (CGEN_CPU_DESC cd, const char **strp,
   return 0;
 }
 
+static const char *
+parse_signed4n (CGEN_CPU_DESC cd, const char **strp,
+               int opindex, signed long *valuep)
+{
+  const char *errmsg = 0;
+  signed long value;
+  long have_zero = 0;
+
+  if (strncmp (*strp, "0x0", 3) == 0 
+      || (**strp == '0' && *(*strp + 1) != 'x'))
+    have_zero = 1;
+
+  PARSE_SIGNED;
+
+  if (value < -7 || value > 8)
+    return _("Immediate is out of range -7 to 8");
+
+  /* If this field may require a relocation then use larger dsp16.  */
+  if (! have_zero && value == 0)
+    return _("Immediate is out of range -7 to 8");
+
+  *valuep = -value;
+  return 0;
+}
+
 static const char *
 parse_signed8 (CGEN_CPU_DESC cd, const char **strp,
               int opindex, signed long *valuep)
@@ -433,6 +462,26 @@ parse_unsigned24 (CGEN_CPU_DESC cd, const char **strp,
   return 0;
 }
 
+/* This should only be used for #imm->reg.  */
+static const char *
+parse_signed24 (CGEN_CPU_DESC cd, const char **strp,
+                int opindex, signed long *valuep)
+{
+  const char *errmsg = 0;
+  signed long value;
+
+  PARSE_SIGNED;
+
+  if (value <= 0xffffff && value > 0x7fffff)
+    value -= 0x1000000;
+
+  if (value > 0xffffff)
+    return _("dsp:24 immediate is out of range");
+
+  *valuep = value;
+  return 0;
+}
+
 static const char *
 parse_signed32 (CGEN_CPU_DESC cd, const char **strp,
                int opindex, signed long *valuep)
@@ -775,14 +824,14 @@ m32c_cgen_insn_supported (CGEN_CPU_DESC cd,
                          const CGEN_INSN *insn)
 {
   int machs = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH);
-  int isas = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_ISA);
+  CGEN_BITSET isas = CGEN_INSN_BITSET_ATTR_VALUE (insn, CGEN_INSN_ISA);
 
   /* If attributes are absent, assume no restriction.  */
   if (machs == 0)
     machs = ~0;
 
   return ((machs & cd->machs)
-         && (isas & cd->isas));
+          && cgen_bitset_intersect_p (& isas, cd->isas));
 }
 
 /* Parse a set of registers, R0,R1,A0,A1,SB,FB.  */
@@ -1072,3 +1121,16 @@ print_push_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
 {
   print_regset (cd, dis_info, value, attrs, pc, length, PUSH);
 }
+
+static void
+print_signed4n (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+               void * dis_info,
+               signed long value,
+               unsigned int attrs ATTRIBUTE_UNUSED,
+               bfd_vma pc ATTRIBUTE_UNUSED,
+               int length ATTRIBUTE_UNUSED)
+{
+  disassemble_info *info = dis_info;
+
+  (*info->fprintf_func) (info->stream, "%ld", -value);
+}