* m32c.cpu (mov.w:q): Fix mode.

[deliverable/binutils-gdb.git] / cpu / m32c.opc

diff --git a/cpu/m32c.opc b/cpu/m32c.opc
index 226f8d0a25e6097b29cf5afd55b030fc3d1025a7..62353267f4711ac85f90c226d9412855292af0ea 100644 (file)
--- a/cpu/m32c.opc
+++ b/cpu/m32c.opc
@@ -824,14 +824,14 @@ m32c_cgen_insn_supported (CGEN_CPU_DESC cd,
                          const CGEN_INSN *insn)
 {
   int machs = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH);
-  int isas = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_ISA);
+  CGEN_BITSET isas = CGEN_INSN_BITSET_ATTR_VALUE (insn, CGEN_INSN_ISA);
 
   /* If attributes are absent, assume no restriction.  */
   if (machs == 0)
     machs = ~0;
 
   return ((machs & cd->machs)
-         && (isas & cd->isas));
+          && cgen_bitset_intersect_p (& isas, cd->isas));
 }
 
 /* Parse a set of registers, R0,R1,A0,A1,SB,FB.  */