; OpenRISC 1000 32-bit CPU hardware description. -*- Scheme -*-
-; Copyright 2000-2014 Free Software Foundation, Inc.
+; Copyright 2000-2019 Free Software Foundation, Inc.
; Contributed for OR32 by Johan Rydberg, jrydberg@opencores.org
; Modified by Julius Baxter, juliusbaxter@gmail.com
+; Modified by Andrey Bacherov, avbacherov@opencores.org
;
; This program is free software; you can redistribute it and/or modify
; it under the terms of the GNU General Public License as published by
(comment "program counter")
(attrs PC (MACH ORBIS-MACHS))
(type pc UWI)
+ (get () (raw-reg h-pc))
+ (set (newval) (sequence ()
+ (set (reg h-sys-ppc) (raw-reg h-pc))
+ (set (raw-reg h-pc) newval)
+ ))
)
(define-pmacro REG-INDICES
(fp 2))
)
+;
+; Hardware: [S]pecial [P]urpose [R]egisters
+;
+(define-hardware
+ (name h-spr) (comment "special purpose registers")
+ (attrs VIRTUAL (MACH ORBIS-MACHS))
+ (type register UWI (#x20000))
+ (get (index) (c-call UWI "@cpu@_h_spr_get_raw" index))
+ (set (index newval) (c-call VOID "@cpu@_h_spr_set_raw" index newval))
+)
+
+(define-pmacro spr-shift 11)
+(define-pmacro (spr-address spr-group spr-index)
+ (or (sll UWI (enum UWI (.sym "SPR-GROUP-" spr-group)) spr-shift)
+ (enum UWI (.sym "SPR-INDEX-" spr-group "-" spr-index))))
+
+;
+; Hardware: [G]enepral [P]urpose [R]egisters
+;
+(define-hardware
+ (name h-gpr) (comment "general registers")
+ (attrs (MACH ORBIS-MACHS))
+ (type register UWI (32))
+ (indices keyword "" REG-INDICES)
+ (get (index) (reg UWI h-spr (add index (spr-address SYS GPR0))))
+ (set (index newval) (set UWI (reg UWI h-spr (add index (spr-address SYS GPR0))) newval))
+ )
+
+;
+; Hardware: virtual registerts for FPU (single precision)
+; mapped to GPRs
+;
(define-hardware
(name h-fsr)
(comment "floating point registers (single, virtual)")
(set (index newval) (set UWI (reg h-gpr index) (zext UWI (subword SI newval 0))))
)
+;
+; Hardware: virtual registerts for FPU (double precision)
+; mapped to GPRs
+;
(define-hardware
- (name h-fdr) (comment "floating point registers (double, virtual)")
+ (name h-fdr)
+ (comment "or64 floating point registers (double, virtual)")
(attrs VIRTUAL (MACH ORFPX64-MACHS))
(type register DF (32))
(indices keyword "" REG-INDICES)
(set (index newval) (set UDI (reg h-gpr index) (zext UDI (subword DI newval 0))))
)
-(define-hardware
- (name h-spr) (comment "special purpose registers")
- (attrs VIRTUAL (MACH ORBIS-MACHS))
- (type register UWI (#x20000))
- (get (index) (c-call UWI "@cpu@_h_spr_get_raw" index))
- (set (index newval) (c-call VOID "@cpu@_h_spr_set_raw" index newval))
+;
+; Register pairs are offset by 2 for registers r16 and above. This is to
+; be able to allow registers to be call saved in GCC across function calls.
+;
+(define-pmacro (reg-pair-reg-lo index)
+ (and index (const #x1f))
)
-(define-pmacro spr-shift 11)
-(define-pmacro (spr-address spr-group spr-index)
- (or (sll UWI (enum UWI (.sym "SPR-GROUP-" spr-group)) spr-shift)
- (enum UWI (.sym "SPR-INDEX-" spr-group "-" spr-index))))
+(define-pmacro (reg-pair-reg-hi index)
+ (add (and index (const #x1f))
+ (if (eq (sra index (const 5))
+ (const 1))
+ (const 2)
+ (const 1)
+ )
+ )
+)
+
+;
+; Hardware: vrtual registers for double precision floating point
+; operands on 32-bit machines
+; mapped to GPRs
+;
+(define-hardware
+ (name h-fd32r)
+ (comment "or32 floating point registers (double, virtual)")
+ (attrs VIRTUAL (MACH ORFPX64A32-MACHS))
+ (type register DF (32))
+ (get (index) (join DF SI
+ (reg h-gpr (reg-pair-reg-lo index))
+ (reg h-gpr (reg-pair-reg-hi index))))
+ (set (index newval)
+ (sequence ()
+ (set (reg h-gpr (reg-pair-reg-lo index)) (subword SI newval 0))
+ (set (reg h-gpr (reg-pair-reg-hi index))
+ (subword SI newval 1))))
+)
+;
+; Hardware: vrtual 64-bit integer registers for conversions
+; float64 <-> int64 on 32-bit machines
+; mapped to GPRs
+;
(define-hardware
- (name h-gpr) (comment "general registers")
- (attrs (MACH ORBIS-MACHS))
- (type register UWI (32))
- (indices keyword "" REG-INDICES)
- (get (index) (reg UWI h-spr (add index (spr-address SYS GPR0))))
- (set (index newval) (set UWI (reg UWI h-spr (add index (spr-address SYS GPR0))) newval))
- )
+ (name h-i64r)
+ (comment "or32 double word registers (int64, virtual)")
+ (attrs VIRTUAL (MACH ORFPX64A32-MACHS))
+ (type register DI (32))
+ (get (index) (join DI SI
+ (reg h-gpr (reg-pair-reg-lo index))
+ (reg h-gpr (reg-pair-reg-hi index))))
+ (set (index newval)
+ (sequence ()
+ (set (reg h-gpr (reg-pair-reg-lo index)) (subword SI newval 0))
+ (set (reg h-gpr (reg-pair-reg-hi index))
+ (subword SI newval 1))))
+)
+
(define-normal-enum
except-number
(SYS DCFGR #x007 "Debug configuration register")
(SYS PCCFGR #x008 "Performance counters configuration register")
(SYS NPC #x010 "Next program counter")
- (SYS SR #x011 "Supervision Regsiter")
+ (SYS SR #x011 "Supervision Register")
(SYS PPC #x012 "Previous program counter")
(SYS FPCSR #x014 "Floating point control status register")
(.unsplice
(define-normal-enum
spr-reg-indices
- "special purpose register indicies"
+ "special purpose register indices"
()
SPR-INDEX-
(.map (.pmacro (args)