Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs

[deliverable/linux.git] / drivers / clk / renesas / r8a7795-cpg-mssr.c

diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c
index b2198aef5ed4291291d30ca1df3cc2ba5ab5c9a0..ca5519c583d4bf57d1c948abc4bf76ee4b8e60c7 100644 (file)
--- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c
@@ -13,6 +13,7 @@
  */
 
 #include <linux/bug.h>
+#include <linux/clk.h>
 #include <linux/clk-provider.h>
 #include <linux/device.h>
 #include <linux/err.h>
@@ -26,6 +27,7 @@
 
 #include "renesas-cpg-mssr.h"
 
+#define CPG_RCKCR      0x240
 
 enum clk_ids {
        /* Core Clock Outputs exported to DT */
@@ -50,6 +52,7 @@ enum clk_ids {
        CLK_S3,
        CLK_SDSRC,
        CLK_SSPSRC,
+       CLK_RINT,
 
        /* Module Clocks */
        MOD_CLK_BASE
@@ -63,8 +66,12 @@ enum r8a7795_clk_types {
        CLK_TYPE_GEN3_PLL3,
        CLK_TYPE_GEN3_PLL4,
        CLK_TYPE_GEN3_SD,
+       CLK_TYPE_GEN3_R,
 };
 
+#define DEF_GEN3_SD(_name, _id, _parent, _offset)      \
+       DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
+
 static const struct cpg_core_clk r8a7795_core_clks[] __initconst = {
        /* External Clock Inputs */
        DEF_INPUT("extal",  CLK_EXTAL),
@@ -102,10 +109,10 @@ static const struct cpg_core_clk r8a7795_core_clks[] __initconst = {
        DEF_FIXED("s3d2",       R8A7795_CLK_S3D2,  CLK_S3,         2, 1),
        DEF_FIXED("s3d4",       R8A7795_CLK_S3D4,  CLK_S3,         4, 1),
 
-       DEF_SD("sd0",           R8A7795_CLK_SD0,   CLK_PLL1_DIV2, 0x0074),
-       DEF_SD("sd1",           R8A7795_CLK_SD1,   CLK_PLL1_DIV2, 0x0078),
-       DEF_SD("sd2",           R8A7795_CLK_SD2,   CLK_PLL1_DIV2, 0x0268),
-       DEF_SD("sd3",           R8A7795_CLK_SD3,   CLK_PLL1_DIV2, 0x026c),
+       DEF_GEN3_SD("sd0",      R8A7795_CLK_SD0,   CLK_PLL1_DIV2, 0x0074),
+       DEF_GEN3_SD("sd1",      R8A7795_CLK_SD1,   CLK_PLL1_DIV2, 0x0078),
+       DEF_GEN3_SD("sd2",      R8A7795_CLK_SD2,   CLK_PLL1_DIV2, 0x0268),
+       DEF_GEN3_SD("sd3",      R8A7795_CLK_SD3,   CLK_PLL1_DIV2, 0x026c),
 
        DEF_FIXED("cl",         R8A7795_CLK_CL,    CLK_PLL1_DIV2, 48, 1),
        DEF_FIXED("cp",         R8A7795_CLK_CP,    CLK_EXTAL,      2, 1),
@@ -113,6 +120,12 @@ static const struct cpg_core_clk r8a7795_core_clks[] __initconst = {
        DEF_DIV6P1("mso",       R8A7795_CLK_MSO,   CLK_PLL1_DIV4, 0x014),
        DEF_DIV6P1("hdmi",      R8A7795_CLK_HDMI,  CLK_PLL1_DIV2, 0x250),
        DEF_DIV6P1("canfd",     R8A7795_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
+       DEF_DIV6P1("csi0",      R8A7795_CLK_CSI0,  CLK_PLL1_DIV4, 0x00c),
+
+       DEF_DIV6_RO("osc",      R8A7795_CLK_OSC,   CLK_EXTAL, CPG_RCKCR, 8),
+       DEF_DIV6_RO("r_int",    CLK_RINT,          CLK_EXTAL, CPG_RCKCR, 32),
+
+       DEF_BASE("r",           R8A7795_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
 };
 
 static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = {
@@ -139,6 +152,7 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = {
        DEF_MOD("usb3-if0",              328,   R8A7795_CLK_S3D1),
        DEF_MOD("usb-dmac0",             330,   R8A7795_CLK_S3D1),
        DEF_MOD("usb-dmac1",             331,   R8A7795_CLK_S3D1),
+       DEF_MOD("rwdt0",                 402,   R8A7795_CLK_R),
        DEF_MOD("intc-ex",               407,   R8A7795_CLK_CP),
        DEF_MOD("intc-ap",               408,   R8A7795_CLK_S3D1),
        DEF_MOD("audmac0",               502,   R8A7795_CLK_S3D4),
@@ -148,6 +162,7 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = {
        DEF_MOD("hscif2",                518,   R8A7795_CLK_S3D1),
        DEF_MOD("hscif1",                519,   R8A7795_CLK_S3D1),
        DEF_MOD("hscif0",                520,   R8A7795_CLK_S3D1),
+       DEF_MOD("pwm",                   523,   R8A7795_CLK_S3D4),
        DEF_MOD("fcpvd3",                600,   R8A7795_CLK_S2D1),
        DEF_MOD("fcpvd2",                601,   R8A7795_CLK_S2D1),
        DEF_MOD("fcpvd1",                602,   R8A7795_CLK_S2D1),
@@ -176,6 +191,10 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = {
        DEF_MOD("ehci1",                 702,   R8A7795_CLK_S3D4),
        DEF_MOD("ehci0",                 703,   R8A7795_CLK_S3D4),
        DEF_MOD("hsusb",                 704,   R8A7795_CLK_S3D4),
+       DEF_MOD("csi21",                 713,   R8A7795_CLK_CSI0),
+       DEF_MOD("csi20",                 714,   R8A7795_CLK_CSI0),
+       DEF_MOD("csi41",                 715,   R8A7795_CLK_CSI0),
+       DEF_MOD("csi40",                 716,   R8A7795_CLK_CSI0),
        DEF_MOD("du3",                   721,   R8A7795_CLK_S2D1),
        DEF_MOD("du2",                   722,   R8A7795_CLK_S2D1),
        DEF_MOD("du1",                   723,   R8A7795_CLK_S2D1),
@@ -183,6 +202,14 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = {
        DEF_MOD("lvds",                  727,   R8A7795_CLK_S2D1),
        DEF_MOD("hdmi1",                 728,   R8A7795_CLK_HDMI),
        DEF_MOD("hdmi0",                 729,   R8A7795_CLK_HDMI),
+       DEF_MOD("vin7",                  804,   R8A7795_CLK_S2D1),
+       DEF_MOD("vin6",                  805,   R8A7795_CLK_S2D1),
+       DEF_MOD("vin5",                  806,   R8A7795_CLK_S2D1),
+       DEF_MOD("vin4",                  807,   R8A7795_CLK_S2D1),
+       DEF_MOD("vin3",                  808,   R8A7795_CLK_S2D1),
+       DEF_MOD("vin2",                  809,   R8A7795_CLK_S2D1),
+       DEF_MOD("vin1",                  810,   R8A7795_CLK_S2D1),
+       DEF_MOD("vin0",                  811,   R8A7795_CLK_S2D1),
        DEF_MOD("etheravb",              812,   R8A7795_CLK_S3D2),
        DEF_MOD("sata0",                 815,   R8A7795_CLK_S3D2),
        DEF_MOD("gpio7",                 905,   R8A7795_CLK_CP),
@@ -578,6 +605,18 @@ struct clk * __init r8a7795_cpg_clk_register(struct device *dev,
        case CLK_TYPE_GEN3_SD:
                return cpg_sd_clk_register(core, base, __clk_get_name(parent));
 
+       case CLK_TYPE_GEN3_R:
+               /* RINT is default. Only if EXTALR is populated, we switch to it */
+               value = readl(base + CPG_RCKCR) & 0x3f;
+
+               if (clk_get_rate(clks[CLK_EXTALR])) {
+                       parent = clks[CLK_EXTALR];
+                       value |= BIT(15);
+               }
+
+               writel(value, base + CPG_RCKCR);
+               break;
+
        default:
                return ERR_PTR(-EINVAL);
        }