drm/i915: Engage the DP scramble reset for pipe C on CHV

[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_reg.h

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index aa628998f83601ad1a9091d229721bf02565a362..451d526ea5d548ff802d5aaac0cb7792da9df0c4 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2789,7 +2789,8 @@ enum punit_power_well {
 #define   DC_BALANCE_RESET                     (1 << 25)
 #define PORT_DFT2_G4X          (dev_priv->info.display_mmio_offset + 0x61154)
 #define   DC_BALANCE_RESET_VLV                 (1 << 31)
-#define   PIPE_SCRAMBLE_RESET_MASK             (0x3 << 0)
+#define   PIPE_SCRAMBLE_RESET_MASK             ((1 << 14) | (0x3 << 0))
+#define   PIPE_C_SCRAMBLE_RESET                        (1 << 14) /* chv */
 #define   PIPE_B_SCRAMBLE_RESET                        (1 << 1)
 #define   PIPE_A_SCRAMBLE_RESET                        (1 << 0)