Merge branch 'drm-intel-fixes' into drm-intel-next

[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_reg.h

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a7f7a347c7003d8e0562199bdf8ff65b37f8468a..be67a596eee5b8b1504e0f21be9755b2616d376d 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -579,6 +579,7 @@
 #define   DPFC_CTL_PLANEA      (0<<30)
 #define   DPFC_CTL_PLANEB      (1<<30)
 #define   DPFC_CTL_FENCE_EN    (1<<29)
+#define   DPFC_CTL_PERSISTENT_MODE     (1<<25)
 #define   DPFC_SR_EN           (1<<10)
 #define   DPFC_CTL_LIMIT_1X    (0<<6)
 #define   DPFC_CTL_LIMIT_2X    (1<<6)
@@ -3381,6 +3382,7 @@
 #define  FORCEWAKE_ACK                         0x130090
 
 #define  GT_FIFO_FREE_ENTRIES                  0x120008
+#define    GT_FIFO_NUM_RESERVED_ENTRIES                20
 
 #define GEN6_RPNSWREQ                          0xA008
 #define   GEN6_TURBO_DISABLE                   (1<<31)
@@ -3455,7 +3457,9 @@
 #define GEN6_PCODE_MAILBOX                     0x138124
 #define   GEN6_PCODE_READY                     (1<<31)
 #define   GEN6_READ_OC_PARAMS                  0xc
-#define   GEN6_PCODE_WRITE_MIN_FREQ_TABLE      0x9
+#define   GEN6_PCODE_WRITE_MIN_FREQ_TABLE      0x8
+#define   GEN6_PCODE_READ_MIN_FREQ_TABLE       0x9
 #define GEN6_PCODE_DATA                                0x138128
+#define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT       8
 
 #endif /* _I915_REG_H_ */