drm/i915: Use atomics to manipulate obj->frontbuffer_bits

[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_vgpu.h

diff --git a/drivers/gpu/drm/i915/i915_vgpu.h b/drivers/gpu/drm/i915/i915_vgpu.h
index 3c83b47b5f699756a4d3199a94a6e6500e70577f..3c3b2d24e830447ff0023b47bf7a38d21f5048cc 100644 (file)
--- a/drivers/gpu/drm/i915/i915_vgpu.h
+++ b/drivers/gpu/drm/i915/i915_vgpu.h
@@ -24,94 +24,10 @@
 #ifndef _I915_VGPU_H_
 #define _I915_VGPU_H_
 
-/* The MMIO offset of the shared info between guest and host emulator */
-#define VGT_PVINFO_PAGE        0x78000
-#define VGT_PVINFO_SIZE        0x1000
+#include "i915_pvinfo.h"
 
-/*
- * The following structure pages are defined in GEN MMIO space
- * for virtualization. (One page for now)
- */
-#define VGT_MAGIC         0x4776544776544776ULL        /* 'vGTvGTvG' */
-#define VGT_VERSION_MAJOR 1
-#define VGT_VERSION_MINOR 0
-
-#define INTEL_VGT_IF_VERSION_ENCODE(major, minor) ((major) << 16 | (minor))
-#define INTEL_VGT_IF_VERSION \
-       INTEL_VGT_IF_VERSION_ENCODE(VGT_VERSION_MAJOR, VGT_VERSION_MINOR)
-
-/*
- * notifications from guest to vgpu device model
- */
-enum vgt_g2v_type {
-       VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE = 2,
-       VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY,
-       VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE,
-       VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY,
-       VGT_G2V_EXECLIST_CONTEXT_CREATE,
-       VGT_G2V_EXECLIST_CONTEXT_DESTROY,
-       VGT_G2V_MAX,
-};
-
-struct vgt_if {
-       uint64_t magic;         /* VGT_MAGIC */
-       uint16_t version_major;
-       uint16_t version_minor;
-       uint32_t vgt_id;        /* ID of vGT instance */
-       uint32_t rsv1[12];      /* pad to offset 0x40 */
-       /*
-        *  Data structure to describe the balooning info of resources.
-        *  Each VM can only have one portion of continuous area for now.
-        *  (May support scattered resource in future)
-        *  (starting from offset 0x40)
-        */
-       struct {
-               /* Aperture register balooning */
-               struct {
-                       uint32_t base;
-                       uint32_t size;
-               } mappable_gmadr;       /* aperture */
-               /* GMADR register balooning */
-               struct {
-                       uint32_t base;
-                       uint32_t size;
-               } nonmappable_gmadr;    /* non aperture */
-               /* allowed fence registers */
-               uint32_t fence_num;
-               uint32_t rsv2[3];
-       } avail_rs;             /* available/assigned resource */
-       uint32_t rsv3[0x200 - 24];      /* pad to half page */
-       /*
-        * The bottom half page is for response from Gfx driver to hypervisor.
-        */
-       uint32_t rsv4;
-       uint32_t display_ready; /* ready for display owner switch */
-
-       uint32_t rsv5[4];
-
-       uint32_t g2v_notify;
-       uint32_t rsv6[7];
-
-       struct {
-               uint32_t lo;
-               uint32_t hi;
-       } pdp[4];
-
-       uint32_t execlist_context_descriptor_lo;
-       uint32_t execlist_context_descriptor_hi;
-
-       uint32_t  rsv7[0x200 - 24];    /* pad to one page */
-} __packed;
-
-#define vgtif_reg(x) \
-       _MMIO((VGT_PVINFO_PAGE + (long)&((struct vgt_if *)NULL)->x))
-
-/* vGPU display status to be used by the host side */
-#define VGT_DRV_DISPLAY_NOT_READY 0
-#define VGT_DRV_DISPLAY_READY     1  /* ready for display switch */
-
-extern void i915_check_vgpu(struct drm_device *dev);
-extern int intel_vgt_balloon(struct drm_device *dev);
-extern void intel_vgt_deballoon(void);
+void i915_check_vgpu(struct drm_i915_private *dev_priv);
+int intel_vgt_balloon(struct drm_i915_private *dev_priv);
+void intel_vgt_deballoon(struct drm_i915_private *dev_priv);
 
 #endif /* _I915_VGPU_H_ */