drm/i915: State readout and cross-checking for ddi_pll_sel

[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 6332d9dda00fc5021b09279053c55063ce533511..e26df678340676eef2610097b2ed3a268920ff93 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7570,6 +7570,35 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
        return 0;
 }
 
+static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
+                                      struct intel_crtc_config *pipe_config)
+{
+       struct drm_device *dev = crtc->base.dev;
+       struct drm_i915_private *dev_priv = dev->dev_private;
+       enum port port;
+       uint32_t tmp;
+
+       tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
+
+       port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
+
+       pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
+       /*
+        * Haswell has only FDI/PCH transcoder A. It is which is connected to
+        * DDI E. So just check whether this pipe is wired to DDI E and whether
+        * the PCH transcoder is on.
+        */
+       if ((port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
+               pipe_config->has_pch_encoder = true;
+
+               tmp = I915_READ(FDI_RX_CTL(PIPE_A));
+               pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
+                                         FDI_DP_PORT_WIDTH_SHIFT) + 1;
+
+               ironlake_get_fdi_m_n_config(crtc, pipe_config);
+       }
+}
+
 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
                                    struct intel_crtc_config *pipe_config)
 {
@@ -7615,22 +7644,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
        if (!(tmp & PIPECONF_ENABLE))
                return false;
 
-       /*
-        * Haswell has only FDI/PCH transcoder A. It is which is connected to
-        * DDI E. So just check whether this pipe is wired to DDI E and whether
-        * the PCH transcoder is on.
-        */
-       tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
-       if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
-           I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
-               pipe_config->has_pch_encoder = true;
-
-               tmp = I915_READ(FDI_RX_CTL(PIPE_A));
-               pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
-                                         FDI_DP_PORT_WIDTH_SHIFT) + 1;
-
-               ironlake_get_fdi_m_n_config(crtc, pipe_config);
-       }
+       haswell_get_ddi_port_state(crtc, pipe_config);
 
        intel_get_pipe_timings(crtc, pipe_config);
 
@@ -10409,6 +10423,8 @@ intel_pipe_config_compare(struct drm_device *dev,
 
        PIPE_CONF_CHECK_I(double_wide);
 
+       PIPE_CONF_CHECK_X(ddi_pll_sel);
+
        PIPE_CONF_CHECK_I(shared_dpll);
        PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
        PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);