drm/i915: implement Haswell DP link train sequence

[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 57dbb49ff5c5ef88ba714128f058050f5417dfee..f6d86492ba3eda4693ee39d79c8d06b1db50bc6b 100644 (file)
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -102,8 +102,6 @@ bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
        return is_pch_edp(intel_dp);
 }
 
-static void intel_dp_start_link_train(struct intel_dp *intel_dp);
-static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
 static void intel_dp_link_down(struct intel_dp *intel_dp);
 
 void
@@ -356,6 +354,29 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
        uint32_t aux_clock_divider;
        int try, precharge;
 
+       if (IS_HASWELL(dev)) {
+               switch (intel_dp->port) {
+               case PORT_A:
+                       ch_ctl = DPA_AUX_CH_CTL;
+                       ch_data = DPA_AUX_CH_DATA1;
+                       break;
+               case PORT_B:
+                       ch_ctl = PCH_DPB_AUX_CH_CTL;
+                       ch_data = PCH_DPB_AUX_CH_DATA1;
+                       break;
+               case PORT_C:
+                       ch_ctl = PCH_DPC_AUX_CH_CTL;
+                       ch_data = PCH_DPC_AUX_CH_DATA1;
+                       break;
+               case PORT_D:
+                       ch_ctl = PCH_DPD_AUX_CH_CTL;
+                       ch_data = PCH_DPD_AUX_CH_DATA1;
+                       break;
+               default:
+                       BUG();
+               }
+       }
+
        intel_dp_check_edp(intel_dp);
        /* The clock divider is based off the hrawclk,
         * and would like to run at 2MHz. So, take the
@@ -793,7 +814,12 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
        intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
                             mode->clock, adjusted_mode->clock, &m_n);
 
-       if (HAS_PCH_SPLIT(dev)) {
+       if (IS_HASWELL(dev)) {
+               I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
+               I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
+               I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
+               I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
+       } else if (HAS_PCH_SPLIT(dev)) {
                I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
                I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
                I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
@@ -812,6 +838,21 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
        }
 }
 
+void intel_dp_init_link_config(struct intel_dp *intel_dp)
+{
+       memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
+       intel_dp->link_configuration[0] = intel_dp->link_bw;
+       intel_dp->link_configuration[1] = intel_dp->lane_count;
+       intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
+       /*
+        * Check for DPCD version > 1.1 and enhanced framing support
+        */
+       if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
+           (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
+               intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
+       }
+}
+
 static void
 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
                  struct drm_display_mode *adjusted_mode)
@@ -864,17 +905,8 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
                intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
                intel_write_eld(encoder, adjusted_mode);
        }
-       memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
-       intel_dp->link_configuration[0] = intel_dp->link_bw;
-       intel_dp->link_configuration[1] = intel_dp->lane_count;
-       intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
-       /*
-        * Check for DPCD version > 1.1 and enhanced framing support
-        */
-       if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
-           (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
-               intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
-       }
+
+       intel_dp_init_link_config(intel_dp);
 
        /* Split out the IBX/CPU vs CPT settings */
 
@@ -1232,7 +1264,7 @@ static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
 }
 
 /* If the sink supports it, try to set the power state appropriately */
-static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
+void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
 {
        int ret, i;
 
@@ -1820,16 +1852,20 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
 }
 
 /* Enable corresponding port and start training pattern 1 */
-static void
+void
 intel_dp_start_link_train(struct intel_dp *intel_dp)
 {
-       struct drm_device *dev = intel_dp->base.base.dev;
+       struct drm_encoder *encoder = &intel_dp->base.base;
+       struct drm_device *dev = encoder->dev;
        int i;
        uint8_t voltage;
        bool clock_recovery = false;
        int voltage_tries, loop_tries;
        uint32_t DP = intel_dp->DP;
 
+       if (IS_HASWELL(dev))
+               intel_ddi_prepare_link_retrain(encoder);
+
        /* Write the link configuration data */
        intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
                                  intel_dp->link_configuration,
@@ -1915,7 +1951,7 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
        intel_dp->DP = DP;
 }
 
-static void
+void
 intel_dp_complete_link_train(struct intel_dp *intel_dp)
 {
        struct drm_device *dev = intel_dp->base.base.dev;
@@ -2001,6 +2037,24 @@ intel_dp_link_down(struct intel_dp *intel_dp)
        struct drm_i915_private *dev_priv = dev->dev_private;
        uint32_t DP = intel_dp->DP;
 
+       /*
+        * DDI code has a strict mode set sequence and we should try to respect
+        * it, otherwise we might hang the machine in many different ways. So we
+        * really should be disabling the port only on a complete crtc_disable
+        * sequence. This function is just called under two conditions on DDI
+        * code:
+        * - Link train failed while doing crtc_enable, and on this case we
+        *   really should respect the mode set sequence and wait for a
+        *   crtc_disable.
+        * - Someone turned the monitor off and intel_dp_check_link_status
+        *   called us. We don't need to disable the whole port on this case, so
+        *   when someone turns the monitor on again,
+        *   intel_ddi_prepare_link_retrain will take care of redoing the link
+        *   train.
+        */
+       if (IS_HASWELL(dev))
+               return;
+
        if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
                return;