drm/i915/bxt: fix WaForceContextSaveRestoreNonCoherent on steppings B0+

[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 8404e0c318e7c124faf77d0aa602c2b12d876cb3..a071b1062e30b84ec10b6cbb883036e81ffde24e 100644 (file)
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -944,39 +944,26 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
                                  DISABLE_PIXEL_MASK_CAMMING);
        }
 
-       if (INTEL_REVID(dev) >= SKL_REVID_C0) {
-               /* WaEnableYV12BugFixInHalfSliceChicken7:skl */
+       if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) >= SKL_REVID_C0) ||
+           IS_BROXTON(dev)) {
+               /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */
                WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
                                  GEN9_ENABLE_YV12_BUGFIX);
        }
 
-       if (INTEL_REVID(dev) <= SKL_REVID_D0) {
-               /*
-                *Use Force Non-Coherent whenever executing a 3D context. This
-                * is a workaround for a possible hang in the unlikely event
-                * a TLB invalidation occurs during a PSD flush.
-                */
-               /* WaForceEnableNonCoherent:skl */
-               WA_SET_BIT_MASKED(HDC_CHICKEN0,
-                                 HDC_FORCE_NON_COHERENT);
-       }
-
-       /* Wa4x4STCOptimizationDisable:skl */
+       /* Wa4x4STCOptimizationDisable:skl,bxt */
        WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
 
-       /* WaDisablePartialResolveInVc:skl */
+       /* WaDisablePartialResolveInVc:skl,bxt */
        WA_SET_BIT_MASKED(CACHE_MODE_1, GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE);
 
-       /* WaCcsTlbPrefetchDisable:skl */
+       /* WaCcsTlbPrefetchDisable:skl,bxt */
        WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
                          GEN9_CCS_TLB_PREFETCH_ENABLE);
 
-       /*
-        * FIXME: don't apply the following on BXT for stepping C. On BXT A0
-        * the flag reads back as 0.
-        */
-       /* WaDisableMaskBasedCammingInRCC:sklC,bxtA */
-       if (INTEL_REVID(dev) == SKL_REVID_C0 || IS_BROXTON(dev))
+       /* WaDisableMaskBasedCammingInRCC:skl,bxt */
+       if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_C0) ||
+           (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0))
                WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
                                  PIXEL_MASK_CAMMING_DISABLE);
 
@@ -1038,6 +1025,17 @@ static int skl_init_workarounds(struct intel_engine_cs *ring)
                WA_SET_BIT_MASKED(HIZ_CHICKEN,
                                  BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
 
+       if (INTEL_REVID(dev) <= SKL_REVID_D0) {
+               /*
+                *Use Force Non-Coherent whenever executing a 3D context. This
+                * is a workaround for a possible hang in the unlikely event
+                * a TLB invalidation occurs during a PSD flush.
+                */
+               /* WaForceEnableNonCoherent:skl */
+               WA_SET_BIT_MASKED(HDC_CHICKEN0,
+                                 HDC_FORCE_NON_COHERENT);
+       }
+
        return skl_tune_iz_hashing(ring);
 }
 
@@ -1045,6 +1043,7 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring)
 {
        struct drm_device *dev = ring->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
+       uint32_t tmp;
 
        gen9_init_workarounds(ring);
 
@@ -1060,8 +1059,10 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring)
        }
 
        /* WaForceContextSaveRestoreNonCoherent:bxt */
-       WA_SET_BIT_MASKED(HDC_CHICKEN0,
-                         HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT);
+       tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
+       if (INTEL_REVID(dev) >= BXT_REVID_B0)
+               tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
+       WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
 
        return 0;
 }