drm/nouveau/gr: convert to new-style nvkm_engine
[deliverable/linux.git] / drivers / gpu / drm / nouveau / nvkm / engine / device / nv30.c
index 3d687d760601ec2a17697d1ebaf0d0ed45960e7a..5a8fd485467a507aed6bc7c3af4fd4440ef3310b 100644 (file)
@@ -28,97 +28,22 @@ nv30_identify(struct nvkm_device *device)
 {
        switch (device->chipset) {
        case 0x30:
-               device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
-               device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
-               device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
-               device->oclass[NVDEV_SUBDEV_CLK    ] = &nv04_clk_oclass;
-               device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv20_devinit_oclass;
-               device->oclass[NVDEV_SUBDEV_MC     ] =  nv04_mc_oclass;
-               device->oclass[NVDEV_SUBDEV_BUS    ] =  nv04_bus_oclass;
-               device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
-               device->oclass[NVDEV_SUBDEV_FB     ] =  nv30_fb_oclass;
-               device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv04_instmem_oclass;
-               device->oclass[NVDEV_SUBDEV_MMU    ] = &nv04_mmu_oclass;
-               device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
-               device->oclass[NVDEV_ENGINE_GR     ] = &nv30_gr_oclass;
-               device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
                break;
        case 0x35:
-               device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
-               device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
-               device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
-               device->oclass[NVDEV_SUBDEV_CLK    ] = &nv04_clk_oclass;
-               device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv20_devinit_oclass;
-               device->oclass[NVDEV_SUBDEV_MC     ] =  nv04_mc_oclass;
-               device->oclass[NVDEV_SUBDEV_BUS    ] =  nv04_bus_oclass;
-               device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
-               device->oclass[NVDEV_SUBDEV_FB     ] =  nv35_fb_oclass;
-               device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv04_instmem_oclass;
-               device->oclass[NVDEV_SUBDEV_MMU    ] = &nv04_mmu_oclass;
-               device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
-               device->oclass[NVDEV_ENGINE_GR     ] = &nv35_gr_oclass;
-               device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
                break;
        case 0x31:
-               device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
-               device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
-               device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
-               device->oclass[NVDEV_SUBDEV_CLK    ] = &nv04_clk_oclass;
-               device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv20_devinit_oclass;
-               device->oclass[NVDEV_SUBDEV_MC     ] =  nv04_mc_oclass;
-               device->oclass[NVDEV_SUBDEV_BUS    ] =  nv31_bus_oclass;
-               device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
-               device->oclass[NVDEV_SUBDEV_FB     ] =  nv30_fb_oclass;
-               device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv04_instmem_oclass;
-               device->oclass[NVDEV_SUBDEV_MMU    ] = &nv04_mmu_oclass;
-               device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
-               device->oclass[NVDEV_ENGINE_GR     ] = &nv30_gr_oclass;
                device->oclass[NVDEV_ENGINE_MPEG   ] = &nv31_mpeg_oclass;
-               device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
                break;
        case 0x36:
-               device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
-               device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
-               device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
-               device->oclass[NVDEV_SUBDEV_CLK    ] = &nv04_clk_oclass;
-               device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv20_devinit_oclass;
-               device->oclass[NVDEV_SUBDEV_MC     ] =  nv04_mc_oclass;
-               device->oclass[NVDEV_SUBDEV_BUS    ] =  nv31_bus_oclass;
-               device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
-               device->oclass[NVDEV_SUBDEV_FB     ] =  nv36_fb_oclass;
-               device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv04_instmem_oclass;
-               device->oclass[NVDEV_SUBDEV_MMU    ] = &nv04_mmu_oclass;
-               device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
-               device->oclass[NVDEV_ENGINE_GR     ] = &nv35_gr_oclass;
                device->oclass[NVDEV_ENGINE_MPEG   ] = &nv31_mpeg_oclass;
-               device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
                break;
        case 0x34:
-               device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
-               device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
-               device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
-               device->oclass[NVDEV_SUBDEV_CLK    ] = &nv04_clk_oclass;
-               device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv10_devinit_oclass;
-               device->oclass[NVDEV_SUBDEV_MC     ] =  nv04_mc_oclass;
-               device->oclass[NVDEV_SUBDEV_BUS    ] =  nv31_bus_oclass;
-               device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
-               device->oclass[NVDEV_SUBDEV_FB     ] =  nv10_fb_oclass;
-               device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv04_instmem_oclass;
-               device->oclass[NVDEV_SUBDEV_MMU    ] = &nv04_mmu_oclass;
-               device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
-               device->oclass[NVDEV_ENGINE_GR     ] = &nv34_gr_oclass;
                device->oclass[NVDEV_ENGINE_MPEG   ] = &nv31_mpeg_oclass;
-               device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
                break;
        default:
                return -EINVAL;
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