* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
-#include "gk20a.h"
+#include "gf100.h"
#include "ctxgf100.h"
-#include <nvif/class.h>
#include <subdev/timer.h>
-static struct nvkm_oclass
-gk20a_gr_sclass[] = {
- { FERMI_TWOD_A, &nvkm_object_ofuncs },
- { KEPLER_INLINE_TO_MEMORY_A, &nvkm_object_ofuncs },
- { KEPLER_C, &gf100_fermi_ofuncs, gf100_gr_9097_omthds },
- { KEPLER_COMPUTE_A, &nvkm_object_ofuncs, gf100_gr_90c0_omthds },
- {}
-};
+#include <nvif/class.h>
static void
gk20a_gr_init_dtor(struct gf100_gr_pack *pack)
}
static int
-gk20a_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
- struct nvkm_oclass *oclass, void *data, u32 size,
- struct nvkm_object **pobject)
-{
- int err;
- struct gf100_gr_priv *priv;
- struct gf100_gr_fuc fuc;
-
- err = gf100_gr_ctor(parent, engine, oclass, data, size, pobject);
- if (err)
- return err;
-
- priv = (void *)*pobject;
-
- err = gf100_gr_ctor_fw(priv, "sw_nonctx", &fuc);
- if (err)
- return err;
- priv->fuc_sw_nonctx = gk20a_gr_av_to_init(&fuc);
- gf100_gr_dtor_fw(&fuc);
- if (IS_ERR(priv->fuc_sw_nonctx))
- return PTR_ERR(priv->fuc_sw_nonctx);
-
- err = gf100_gr_ctor_fw(priv, "sw_ctx", &fuc);
- if (err)
- return err;
- priv->fuc_sw_ctx = gk20a_gr_aiv_to_init(&fuc);
- gf100_gr_dtor_fw(&fuc);
- if (IS_ERR(priv->fuc_sw_ctx))
- return PTR_ERR(priv->fuc_sw_ctx);
-
- err = gf100_gr_ctor_fw(priv, "sw_bundle_init", &fuc);
- if (err)
- return err;
- priv->fuc_bundle = gk20a_gr_av_to_init(&fuc);
- gf100_gr_dtor_fw(&fuc);
- if (IS_ERR(priv->fuc_bundle))
- return PTR_ERR(priv->fuc_bundle);
-
- err = gf100_gr_ctor_fw(priv, "sw_method_init", &fuc);
- if (err)
- return err;
- priv->fuc_method = gk20a_gr_av_to_method(&fuc);
- gf100_gr_dtor_fw(&fuc);
- if (IS_ERR(priv->fuc_method))
- return PTR_ERR(priv->fuc_method);
-
- return 0;
-}
-
-static void
-gk20a_gr_dtor(struct nvkm_object *object)
-{
- struct gf100_gr_priv *priv = (void *)object;
-
- gk20a_gr_init_dtor(priv->fuc_method);
- gk20a_gr_init_dtor(priv->fuc_bundle);
- gk20a_gr_init_dtor(priv->fuc_sw_ctx);
- gk20a_gr_init_dtor(priv->fuc_sw_nonctx);
-
- gf100_gr_dtor(object);
-}
-
-static int
-gk20a_gr_wait_mem_scrubbing(struct gf100_gr_priv *priv)
+gk20a_gr_wait_mem_scrubbing(struct gf100_gr *gr)
{
- if (!nv_wait(priv, 0x40910c, 0x6, 0x0)) {
- nv_error(priv, "FECS mem scrubbing timeout\n");
+ struct nvkm_subdev *subdev = &gr->base.engine.subdev;
+ struct nvkm_device *device = subdev->device;
+
+ if (nvkm_msec(device, 2000,
+ if (!(nvkm_rd32(device, 0x40910c) & 0x00000006))
+ break;
+ ) < 0) {
+ nvkm_error(subdev, "FECS mem scrubbing timeout\n");
return -ETIMEDOUT;
}
- if (!nv_wait(priv, 0x41a10c, 0x6, 0x0)) {
- nv_error(priv, "GPCCS mem scrubbing timeout\n");
+ if (nvkm_msec(device, 2000,
+ if (!(nvkm_rd32(device, 0x41a10c) & 0x00000006))
+ break;
+ ) < 0) {
+ nvkm_error(subdev, "GPCCS mem scrubbing timeout\n");
return -ETIMEDOUT;
}
}
static void
-gk20a_gr_set_hww_esr_report_mask(struct gf100_gr_priv *priv)
+gk20a_gr_set_hww_esr_report_mask(struct gf100_gr *gr)
{
- nv_wr32(priv, 0x419e44, 0x1ffffe);
- nv_wr32(priv, 0x419e4c, 0x7f);
+ struct nvkm_device *device = gr->base.engine.subdev.device;
+ nvkm_wr32(device, 0x419e44, 0x1ffffe);
+ nvkm_wr32(device, 0x419e4c, 0x7f);
}
-static int
-gk20a_gr_init(struct nvkm_object *object)
+int
+gk20a_gr_init(struct gf100_gr *gr)
{
- struct gk20a_gr_oclass *oclass = (void *)object->oclass;
- struct gf100_gr_priv *priv = (void *)object;
- const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total);
+ struct nvkm_device *device = gr->base.engine.subdev.device;
+ const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total);
u32 data[TPC_MAX / 8] = {};
u8 tpcnr[GPC_MAX];
int gpc, tpc;
int ret, i;
- ret = nvkm_gr_init(&priv->base);
- if (ret)
- return ret;
-
/* Clear SCC RAM */
- nv_wr32(priv, 0x40802c, 0x1);
+ nvkm_wr32(device, 0x40802c, 0x1);
- gf100_gr_mmio(priv, priv->fuc_sw_nonctx);
+ gf100_gr_mmio(gr, gr->fuc_sw_nonctx);
- ret = gk20a_gr_wait_mem_scrubbing(priv);
+ ret = gk20a_gr_wait_mem_scrubbing(gr);
if (ret)
return ret;
- ret = gf100_gr_wait_idle(priv);
+ ret = gf100_gr_wait_idle(gr);
if (ret)
return ret;
/* MMU debug buffer */
- nv_wr32(priv, 0x100cc8, priv->unk4188b4->addr >> 8);
- nv_wr32(priv, 0x100ccc, priv->unk4188b8->addr >> 8);
+ nvkm_wr32(device, 0x100cc8, nvkm_memory_addr(gr->unk4188b4) >> 8);
+ nvkm_wr32(device, 0x100ccc, nvkm_memory_addr(gr->unk4188b8) >> 8);
- if (oclass->init_gpc_mmu)
- oclass->init_gpc_mmu(priv);
+ if (gr->func->init_gpc_mmu)
+ gr->func->init_gpc_mmu(gr);
/* Set the PE as stream master */
- nv_mask(priv, 0x503018, 0x1, 0x1);
+ nvkm_mask(device, 0x503018, 0x1, 0x1);
/* Zcull init */
memset(data, 0x00, sizeof(data));
- memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr));
- for (i = 0, gpc = -1; i < priv->tpc_total; i++) {
+ memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr));
+ for (i = 0, gpc = -1; i < gr->tpc_total; i++) {
do {
- gpc = (gpc + 1) % priv->gpc_nr;
+ gpc = (gpc + 1) % gr->gpc_nr;
} while (!tpcnr[gpc]);
- tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--;
+ tpc = gr->tpc_nr[gpc] - tpcnr[gpc]--;
data[i / 8] |= tpc << ((i % 8) * 4);
}
- nv_wr32(priv, GPC_BCAST(0x0980), data[0]);
- nv_wr32(priv, GPC_BCAST(0x0984), data[1]);
- nv_wr32(priv, GPC_BCAST(0x0988), data[2]);
- nv_wr32(priv, GPC_BCAST(0x098c), data[3]);
-
- for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
- nv_wr32(priv, GPC_UNIT(gpc, 0x0914),
- priv->magic_not_rop_nr << 8 | priv->tpc_nr[gpc]);
- nv_wr32(priv, GPC_UNIT(gpc, 0x0910), 0x00040000 |
- priv->tpc_total);
- nv_wr32(priv, GPC_UNIT(gpc, 0x0918), magicgpc918);
+ nvkm_wr32(device, GPC_BCAST(0x0980), data[0]);
+ nvkm_wr32(device, GPC_BCAST(0x0984), data[1]);
+ nvkm_wr32(device, GPC_BCAST(0x0988), data[2]);
+ nvkm_wr32(device, GPC_BCAST(0x098c), data[3]);
+
+ for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
+ nvkm_wr32(device, GPC_UNIT(gpc, 0x0914),
+ gr->magic_not_rop_nr << 8 | gr->tpc_nr[gpc]);
+ nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 |
+ gr->tpc_total);
+ nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918);
}
- nv_wr32(priv, GPC_BCAST(0x3fd4), magicgpc918);
+ nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918);
/* Enable FIFO access */
- nv_wr32(priv, 0x400500, 0x00010001);
+ nvkm_wr32(device, 0x400500, 0x00010001);
/* Enable interrupts */
- nv_wr32(priv, 0x400100, 0xffffffff);
- nv_wr32(priv, 0x40013c, 0xffffffff);
+ nvkm_wr32(device, 0x400100, 0xffffffff);
+ nvkm_wr32(device, 0x40013c, 0xffffffff);
/* Enable FECS error interrupts */
- nv_wr32(priv, 0x409c24, 0x000f0000);
+ nvkm_wr32(device, 0x409c24, 0x000f0000);
/* Enable hardware warning exceptions */
- nv_wr32(priv, 0x404000, 0xc0000000);
- nv_wr32(priv, 0x404600, 0xc0000000);
+ nvkm_wr32(device, 0x404000, 0xc0000000);
+ nvkm_wr32(device, 0x404600, 0xc0000000);
- if (oclass->set_hww_esr_report_mask)
- oclass->set_hww_esr_report_mask(priv);
+ if (gr->func->set_hww_esr_report_mask)
+ gr->func->set_hww_esr_report_mask(gr);
/* Enable TPC exceptions per GPC */
- nv_wr32(priv, 0x419d0c, 0x2);
- nv_wr32(priv, 0x41ac94, (((1 << priv->tpc_total) - 1) & 0xff) << 16);
+ nvkm_wr32(device, 0x419d0c, 0x2);
+ nvkm_wr32(device, 0x41ac94, (((1 << gr->tpc_total) - 1) & 0xff) << 16);
/* Reset and enable all exceptions */
- nv_wr32(priv, 0x400108, 0xffffffff);
- nv_wr32(priv, 0x400138, 0xffffffff);
- nv_wr32(priv, 0x400118, 0xffffffff);
- nv_wr32(priv, 0x400130, 0xffffffff);
- nv_wr32(priv, 0x40011c, 0xffffffff);
- nv_wr32(priv, 0x400134, 0xffffffff);
+ nvkm_wr32(device, 0x400108, 0xffffffff);
+ nvkm_wr32(device, 0x400138, 0xffffffff);
+ nvkm_wr32(device, 0x400118, 0xffffffff);
+ nvkm_wr32(device, 0x400130, 0xffffffff);
+ nvkm_wr32(device, 0x40011c, 0xffffffff);
+ nvkm_wr32(device, 0x400134, 0xffffffff);
+
+ gf100_gr_zbc_init(gr);
+
+ return gf100_gr_init_ctxctl(gr);
+}
+
+void
+gk20a_gr_dtor(struct gf100_gr *gr)
+{
+ gk20a_gr_init_dtor(gr->fuc_method);
+ gk20a_gr_init_dtor(gr->fuc_bundle);
+ gk20a_gr_init_dtor(gr->fuc_sw_ctx);
+ gk20a_gr_init_dtor(gr->fuc_sw_nonctx);
+}
+
+int
+gk20a_gr_new_(const struct gf100_gr_func *func, struct nvkm_device *device,
+ int index, struct nvkm_gr **pgr)
+{
+ struct gf100_gr_fuc fuc;
+ struct gf100_gr *gr;
+ int ret;
+
+ if (!(gr = kzalloc(sizeof(*gr), GFP_KERNEL)))
+ return -ENOMEM;
+ *pgr = &gr->base;
+
+ ret = gf100_gr_ctor(func, device, index, gr);
+ if (ret)
+ return ret;
+
+ ret = gf100_gr_ctor_fw(gr, "sw_nonctx", &fuc);
+ if (ret)
+ return ret;
+ gr->fuc_sw_nonctx = gk20a_gr_av_to_init(&fuc);
+ gf100_gr_dtor_fw(&fuc);
+ if (IS_ERR(gr->fuc_sw_nonctx))
+ return PTR_ERR(gr->fuc_sw_nonctx);
+
+ ret = gf100_gr_ctor_fw(gr, "sw_ctx", &fuc);
+ if (ret)
+ return ret;
+ gr->fuc_sw_ctx = gk20a_gr_aiv_to_init(&fuc);
+ gf100_gr_dtor_fw(&fuc);
+ if (IS_ERR(gr->fuc_sw_ctx))
+ return PTR_ERR(gr->fuc_sw_ctx);
+
+ ret = gf100_gr_ctor_fw(gr, "sw_bundle_init", &fuc);
+ if (ret)
+ return ret;
+ gr->fuc_bundle = gk20a_gr_av_to_init(&fuc);
+ gf100_gr_dtor_fw(&fuc);
+ if (IS_ERR(gr->fuc_bundle))
+ return PTR_ERR(gr->fuc_bundle);
- gf100_gr_zbc_init(priv);
+ ret = gf100_gr_ctor_fw(gr, "sw_method_init", &fuc);
+ if (ret)
+ return ret;
+ gr->fuc_method = gk20a_gr_av_to_method(&fuc);
+ gf100_gr_dtor_fw(&fuc);
+ if (IS_ERR(gr->fuc_method))
+ return PTR_ERR(gr->fuc_method);
- return gf100_gr_init_ctxctl(priv);
+ return 0;
}
-struct nvkm_oclass *
-gk20a_gr_oclass = &(struct gk20a_gr_oclass) {
- .gf100 = {
- .base.handle = NV_ENGINE(GR, 0xea),
- .base.ofuncs = &(struct nvkm_ofuncs) {
- .ctor = gk20a_gr_ctor,
- .dtor = gk20a_gr_dtor,
- .init = gk20a_gr_init,
- .fini = _nvkm_gr_fini,
- },
- .cclass = &gk20a_grctx_oclass,
- .sclass = gk20a_gr_sclass,
- .ppc_nr = 1,
- },
+static const struct gf100_gr_func
+gk20a_gr = {
+ .dtor = gk20a_gr_dtor,
+ .init = gk20a_gr_init,
.set_hww_esr_report_mask = gk20a_gr_set_hww_esr_report_mask,
-}.gf100.base;
+ .ppc_nr = 1,
+ .grctx = &gk20a_grctx,
+ .sclass = {
+ { -1, -1, FERMI_TWOD_A },
+ { -1, -1, KEPLER_INLINE_TO_MEMORY_A },
+ { -1, -1, KEPLER_C, &gf100_fermi },
+ { -1, -1, KEPLER_COMPUTE_A },
+ {}
+ }
+};
+
+int
+gk20a_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
+{
+ return gk20a_gr_new_(&gk20a_gr, device, index, pgr);
+}
projects / deliverable / linux.git / blobdiff