drivers:net: Convert dma_alloc_coherent(...__GFP_ZERO) to dma_zalloc_coherent

[deliverable/linux.git] / drivers / net / ethernet / broadcom / tg3.c

diff --git a/drivers/net/ethernet/broadcom/tg3.c b/drivers/net/ethernet/broadcom/tg3.c
index 0da2214ef1b9e895903612809b21ed070cf32fa3..2e55ee29cf13cc3e71c863d64f6a6f1571ad00df 100644 (file)
--- a/drivers/net/ethernet/broadcom/tg3.c
+++ b/drivers/net/ethernet/broadcom/tg3.c
@@ -94,10 +94,10 @@ static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
 
 #define DRV_MODULE_NAME                "tg3"
 #define TG3_MAJ_NUM                    3
-#define TG3_MIN_NUM                    132
+#define TG3_MIN_NUM                    133
 #define DRV_MODULE_VERSION     \
        __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
-#define DRV_MODULE_RELDATE     "May 21, 2013"
+#define DRV_MODULE_RELDATE     "Jul 29, 2013"
 
 #define RESET_KIND_SHUTDOWN    0
 #define RESET_KIND_INIT                1
@@ -4226,8 +4226,6 @@ static int tg3_power_down_prepare(struct tg3 *tp)
 
 static void tg3_power_down(struct tg3 *tp)
 {
-       tg3_power_down_prepare(tp);
-
        pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE));
        pci_set_power_state(tp->pdev, PCI_D3hot);
 }
@@ -6095,10 +6093,12 @@ static u64 tg3_refclk_read(struct tg3 *tp)
 /* tp->lock must be held */
 static void tg3_refclk_write(struct tg3 *tp, u64 newval)
 {
-       tw32(TG3_EAV_REF_CLCK_CTL, TG3_EAV_REF_CLCK_CTL_STOP);
+       u32 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL);
+
+       tw32(TG3_EAV_REF_CLCK_CTL, clock_ctl | TG3_EAV_REF_CLCK_CTL_STOP);
        tw32(TG3_EAV_REF_CLCK_LSB, newval & 0xffffffff);
        tw32(TG3_EAV_REF_CLCK_MSB, newval >> 32);
-       tw32_f(TG3_EAV_REF_CLCK_CTL, TG3_EAV_REF_CLCK_CTL_RESUME);
+       tw32_f(TG3_EAV_REF_CLCK_CTL, clock_ctl | TG3_EAV_REF_CLCK_CTL_RESUME);
 }
 
 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync);
@@ -6214,6 +6214,59 @@ static int tg3_ptp_settime(struct ptp_clock_info *ptp,
 static int tg3_ptp_enable(struct ptp_clock_info *ptp,
                          struct ptp_clock_request *rq, int on)
 {
+       struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
+       u32 clock_ctl;
+       int rval = 0;
+
+       switch (rq->type) {
+       case PTP_CLK_REQ_PEROUT:
+               if (rq->perout.index != 0)
+                       return -EINVAL;
+
+               tg3_full_lock(tp, 0);
+               clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL);
+               clock_ctl &= ~TG3_EAV_CTL_TSYNC_GPIO_MASK;
+
+               if (on) {
+                       u64 nsec;
+
+                       nsec = rq->perout.start.sec * 1000000000ULL +
+                              rq->perout.start.nsec;
+
+                       if (rq->perout.period.sec || rq->perout.period.nsec) {
+                               netdev_warn(tp->dev,
+                                           "Device supports only a one-shot timesync output, period must be 0\n");
+                               rval = -EINVAL;
+                               goto err_out;
+                       }
+
+                       if (nsec & (1ULL << 63)) {
+                               netdev_warn(tp->dev,
+                                           "Start value (nsec) is over limit. Maximum size of start is only 63 bits\n");
+                               rval = -EINVAL;
+                               goto err_out;
+                       }
+
+                       tw32(TG3_EAV_WATCHDOG0_LSB, (nsec & 0xffffffff));
+                       tw32(TG3_EAV_WATCHDOG0_MSB,
+                            TG3_EAV_WATCHDOG0_EN |
+                            ((nsec >> 32) & TG3_EAV_WATCHDOG_MSB_MASK));
+
+                       tw32(TG3_EAV_REF_CLCK_CTL,
+                            clock_ctl | TG3_EAV_CTL_TSYNC_WDOG0);
+               } else {
+                       tw32(TG3_EAV_WATCHDOG0_MSB, 0);
+                       tw32(TG3_EAV_REF_CLCK_CTL, clock_ctl);
+               }
+
+err_out:
+               tg3_full_unlock(tp);
+               return rval;
+
+       default:
+               break;
+       }
+
        return -EOPNOTSUPP;
 }
 
@@ -6223,7 +6276,7 @@ static const struct ptp_clock_info tg3_ptp_caps = {
        .max_adj        = 250000000,
        .n_alarm        = 0,
        .n_ext_ts       = 0,
-       .n_per_out      = 0,
+       .n_per_out      = 1,
        .pps            = 0,
        .adjfreq        = tg3_ptp_adjfreq,
        .adjtime        = tg3_ptp_adjtime,
@@ -8538,10 +8591,10 @@ static int tg3_mem_rx_acquire(struct tg3 *tp)
                if (!i && tg3_flag(tp, ENABLE_RSS))
                        continue;
 
-               tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev,
-                                                  TG3_RX_RCB_RING_BYTES(tp),
-                                                  &tnapi->rx_rcb_mapping,
-                                                  GFP_KERNEL | __GFP_ZERO);
+               tnapi->rx_rcb = dma_zalloc_coherent(&tp->pdev->dev,
+                                                   TG3_RX_RCB_RING_BYTES(tp),
+                                                   &tnapi->rx_rcb_mapping,
+                                                   GFP_KERNEL);
                if (!tnapi->rx_rcb)
                        goto err_out;
        }
@@ -8590,10 +8643,9 @@ static int tg3_alloc_consistent(struct tg3 *tp)
 {
        int i;
 
-       tp->hw_stats = dma_alloc_coherent(&tp->pdev->dev,
-                                         sizeof(struct tg3_hw_stats),
-                                         &tp->stats_mapping,
-                                         GFP_KERNEL | __GFP_ZERO);
+       tp->hw_stats = dma_zalloc_coherent(&tp->pdev->dev,
+                                          sizeof(struct tg3_hw_stats),
+                                          &tp->stats_mapping, GFP_KERNEL);
        if (!tp->hw_stats)
                goto err_out;
 
@@ -8601,10 +8653,10 @@ static int tg3_alloc_consistent(struct tg3 *tp)
                struct tg3_napi *tnapi = &tp->napi[i];
                struct tg3_hw_status *sblk;
 
-               tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev,
-                                                     TG3_HW_STATUS_SIZE,
-                                                     &tnapi->status_mapping,
-                                                     GFP_KERNEL | __GFP_ZERO);
+               tnapi->hw_status = dma_zalloc_coherent(&tp->pdev->dev,
+                                                      TG3_HW_STATUS_SIZE,
+                                                      &tnapi->status_mapping,
+                                                      GFP_KERNEL);
                if (!tnapi->hw_status)
                        goto err_out;
 
@@ -10367,6 +10419,9 @@ static int tg3_reset_hw(struct tg3 *tp, bool reset_phy)
        if (tg3_flag(tp, 5755_PLUS))
                tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
 
+       if (tg3_asic_rev(tp) == ASIC_REV_5762)
+               tp->rx_mode |= RX_MODE_IPV4_FRAG_FIX;
+
        if (tg3_flag(tp, ENABLE_RSS))
                tp->rx_mode |= RX_MODE_RSS_ENABLE |
                               RX_MODE_RSS_ITBL_HASH_BITS_7 |
@@ -11502,7 +11557,7 @@ static int tg3_close(struct net_device *dev)
        memset(&tp->net_stats_prev, 0, sizeof(tp->net_stats_prev));
        memset(&tp->estats_prev, 0, sizeof(tp->estats_prev));
 
-       tg3_power_down(tp);
+       tg3_power_down_prepare(tp);
 
        tg3_carrier_off(tp);
 
@@ -11724,9 +11779,6 @@ static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
        if (tg3_flag(tp, NO_NVRAM))
                return -EINVAL;
 
-       if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
-               return -EAGAIN;
-
        offset = eeprom->offset;
        len = eeprom->len;
        eeprom->len = 0;
@@ -11784,9 +11836,6 @@ static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
        u8 *buf;
        __be32 start, end;
 
-       if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
-               return -EAGAIN;
-
        if (tg3_flag(tp, NO_NVRAM) ||
            eeprom->magic != TG3_EEPROM_MAGIC)
                return -EINVAL;
@@ -13515,7 +13564,7 @@ static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
                        tg3_phy_start(tp);
        }
        if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
-               tg3_power_down(tp);
+               tg3_power_down_prepare(tp);
 
 }
 
@@ -15917,7 +15966,7 @@ static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent)
         */
        if (tg3_flag(tp, 5780_CLASS)) {
                tg3_flag_set(tp, 40BIT_DMA_BUG);
-               tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
+               tp->msi_cap = tp->pdev->msi_cap;
        } else {
                struct pci_dev *bridge = NULL;
 
@@ -17547,11 +17596,6 @@ static int tg3_init_one(struct pci_dev *pdev,
            tg3_asic_rev(tp) == ASIC_REV_5762)
                tg3_flag_set(tp, PTP_CAPABLE);
 
-       if (tg3_flag(tp, 5717_PLUS)) {
-               /* Resume a low-power mode */
-               tg3_frob_aux_power(tp, false);
-       }
-
        tg3_timer_init(tp);
 
        tg3_carrier_off(tp);
@@ -17755,6 +17799,23 @@ out:
 
 static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume);
 
+static void tg3_shutdown(struct pci_dev *pdev)
+{
+       struct net_device *dev = pci_get_drvdata(pdev);
+       struct tg3 *tp = netdev_priv(dev);
+
+       rtnl_lock();
+       netif_device_detach(dev);
+
+       if (netif_running(dev))
+               dev_close(dev);
+
+       if (system_state == SYSTEM_POWER_OFF)
+               tg3_power_down(tp);
+
+       rtnl_unlock();
+}
+
 /**
  * tg3_io_error_detected - called when PCI error is detected
  * @pdev: Pointer to PCI device
@@ -17914,6 +17975,7 @@ static struct pci_driver tg3_driver = {
        .remove         = tg3_remove_one,
        .err_handler    = &tg3_err_handler,
        .driver.pm      = &tg3_pm_ops,
+       .shutdown       = tg3_shutdown,
 };
 
 module_pci_driver(tg3_driver);