net/mlx5e: Add missing 50G baseSR2 link mode

[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx5 / core / en.h

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en.h b/drivers/net/ethernet/mellanox/mlx5/core/en.h
index e8a6c3325b396c6295db60c833309c4e4102e780..b8732e6d2b6b8f6c1f8876ddbab6c3a75fd157b7 100644 (file)
--- a/drivers/net/ethernet/mellanox/mlx5/core/en.h
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en.h
@@ -79,6 +79,7 @@
 
 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ                 (64 * 1024)
 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC      0x10
+#define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3
 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS      0x20
 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC      0x10
 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS      0x20
@@ -88,6 +89,7 @@
 #define MLX5E_LOG_INDIR_RQT_SIZE       0x7
 #define MLX5E_INDIR_RQT_SIZE           BIT(MLX5E_LOG_INDIR_RQT_SIZE)
 #define MLX5E_MAX_NUM_CHANNELS         (MLX5E_INDIR_RQT_SIZE >> 1)
+#define MLX5E_MAX_NUM_SQS              (MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC)
 #define MLX5E_TX_CQ_POLL_BUDGET        128
 #define MLX5E_UPDATE_STATS_INTERVAL    200 /* msecs */
 #define MLX5E_SQ_BF_BUDGET             16
@@ -143,11 +145,32 @@ struct mlx5e_umr_wqe {
        struct mlx5_wqe_data_seg       data;
 };
 
+static const char mlx5e_priv_flags[][ETH_GSTRING_LEN] = {
+       "rx_cqe_moder",
+};
+
+enum mlx5e_priv_flag {
+       MLX5E_PFLAG_RX_CQE_BASED_MODER = (1 << 0),
+};
+
+#define MLX5E_SET_PRIV_FLAG(priv, pflag, enable)    \
+       do {                                        \
+               if (enable)                         \
+                       priv->pflags |= pflag;      \
+               else                                \
+                       priv->pflags &= ~pflag;     \
+       } while (0)
+
 #ifdef CONFIG_MLX5_CORE_EN_DCB
 #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */
 #define MLX5E_MIN_BW_ALLOC 1   /* Min percentage of BW allocation */
 #endif
 
+struct mlx5e_cq_moder {
+       u16 usec;
+       u16 pkts;
+};
+
 struct mlx5e_params {
        u8  log_sq_size;
        u8  rq_wq_type;
@@ -156,12 +179,11 @@ struct mlx5e_params {
        u8  log_rq_size;
        u16 num_channels;
        u8  num_tc;
+       u8  rx_cq_period_mode;
        bool rx_cqe_compress_admin;
        bool rx_cqe_compress;
-       u16 rx_cq_moderation_usec;
-       u16 rx_cq_moderation_pkts;
-       u16 tx_cq_moderation_usec;
-       u16 tx_cq_moderation_pkts;
+       struct mlx5e_cq_moder rx_cq_moderation;
+       struct mlx5e_cq_moder tx_cq_moderation;
        u16 min_rx_wqes;
        bool lro_en;
        u32 lro_wqe_sz;
@@ -173,6 +195,7 @@ struct mlx5e_params {
 #ifdef CONFIG_MLX5_CORE_EN_DCB
        struct ieee_ets ets;
 #endif
+       bool rx_am_enabled;
 };
 
 struct mlx5e_tstamp {
@@ -191,6 +214,7 @@ struct mlx5e_tstamp {
 enum {
        MLX5E_RQ_STATE_POST_WQES_ENABLE,
        MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS,
+       MLX5E_RQ_STATE_AM,
 };
 
 struct mlx5e_cq {
@@ -198,6 +222,7 @@ struct mlx5e_cq {
        struct mlx5_cqwq           wq;
 
        /* data path - accessed per napi poll */
+       u16                        event_ctr;
        struct napi_struct        *napi;
        struct mlx5_core_cq        mcq;
        struct mlx5e_channel      *channel;
@@ -225,6 +250,30 @@ struct mlx5e_dma_info {
        dma_addr_t      addr;
 };
 
+struct mlx5e_rx_am_stats {
+       int ppms; /* packets per msec */
+       int epms; /* events per msec */
+};
+
+struct mlx5e_rx_am_sample {
+       ktime_t         time;
+       unsigned int    pkt_ctr;
+       u16             event_ctr;
+};
+
+struct mlx5e_rx_am { /* Adaptive Moderation */
+       u8                                      state;
+       struct mlx5e_rx_am_stats                prev_stats;
+       struct mlx5e_rx_am_sample               start_sample;
+       struct work_struct                      work;
+       u8                                      profile_ix;
+       u8                                      mode;
+       u8                                      tune_state;
+       u8                                      steps_right;
+       u8                                      steps_left;
+       u8                                      tired;
+};
+
 struct mlx5e_rq {
        /* data path */
        struct mlx5_wq_ll      wq;
@@ -245,6 +294,8 @@ struct mlx5e_rq {
        unsigned long          state;
        int                    ix;
 
+       struct mlx5e_rx_am     am; /* Adaptive Moderation */
+
        /* control */
        struct mlx5_wq_ctrl    wq_ctrl;
        u8                     wq_type;
@@ -354,6 +405,7 @@ struct mlx5e_sq {
        struct mlx5e_channel      *channel;
        int                        tc;
        struct mlx5e_ico_wqe_info *ico_wqe_info;
+       u32                        rate_limit;
 } ____cacheline_aligned_in_smp;
 
 static inline bool mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n)
@@ -530,6 +582,7 @@ struct mlx5e_priv {
        u32                        indir_rqtn;
        u32                        indir_tirn[MLX5E_NUM_INDIR_TIRS];
        struct mlx5e_direct_tir    direct_tir[MLX5E_MAX_NUM_CHANNELS];
+       u32                        tx_rates[MLX5E_MAX_NUM_SQS];
 
        struct mlx5e_flow_steering fs;
        struct mlx5e_vxlan_db      vxlan;
@@ -540,6 +593,7 @@ struct mlx5e_priv {
        struct work_struct         set_rx_mode_work;
        struct delayed_work        update_stats_work;
 
+       u32                        pflags;
        struct mlx5_core_dev      *mdev;
        struct net_device         *netdev;
        struct mlx5e_stats         stats;
@@ -562,6 +616,7 @@ enum mlx5e_link_mode {
        MLX5E_10GBASE_ER         = 14,
        MLX5E_40GBASE_SR4        = 15,
        MLX5E_40GBASE_LR4        = 16,
+       MLX5E_50GBASE_SR2        = 18,
        MLX5E_100GBASE_CR4       = 20,
        MLX5E_100GBASE_SR4       = 21,
        MLX5E_100GBASE_KR4       = 22,
@@ -612,6 +667,10 @@ void mlx5e_free_rx_fragmented_mpwqe(struct mlx5e_rq *rq,
                                    struct mlx5e_mpw_info *wi);
 struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq);
 
+void mlx5e_rx_am(struct mlx5e_rq *rq);
+void mlx5e_rx_am_work(struct work_struct *work);
+struct mlx5e_cq_moder mlx5e_am_get_def_profile(u8 rx_cq_period_mode);
+
 void mlx5e_update_stats(struct mlx5e_priv *priv);
 
 int mlx5e_create_flow_steering(struct mlx5e_priv *priv);
@@ -647,6 +706,9 @@ void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
                                   int num_channels);
 int mlx5e_get_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed);
 
+void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params,
+                                u8 cq_period_mode);
+
 static inline void mlx5e_tx_notify_hw(struct mlx5e_sq *sq,
                                      struct mlx5_wqe_ctrl_seg *ctrl, int bf_sz)
 {