/******************************************************************************
* Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
- * Linux device driver for RTL8190P / RTL8192E
+ * Linux device driver for RTL8192E
*
* Based on the r8180 driver, which is:
* Copyright 2004-2005 Andrea Merello <andreamrl@tiscali.it>, et al.
* Jerry chuang <wlanfae@realtek.com>
*/
-
-#undef RX_DONT_PASS_UL
-#undef DEBUG_EPROM
-#undef DEBUG_RX_VERBOSE
-#undef DUMMY_RX
-#undef DEBUG_ZERO_RX
-#undef DEBUG_RX_SKB
-#undef DEBUG_TX_FRAG
-#undef DEBUG_RX_FRAG
-#undef DEBUG_TX_FILLDESC
-#undef DEBUG_TX
-#undef DEBUG_IRQ
-#undef DEBUG_RX
-#undef DEBUG_RXALLOC
-#undef DEBUG_REGISTERS
-#undef DEBUG_RING
-#undef DEBUG_IRQ_TASKLET
-#undef DEBUG_TX_ALLOC
-#undef DEBUG_TX_DESC
-
//#define CONFIG_RTL8192_IO_MAP
#include <linux/vmalloc.h>
#include <linux/slab.h>
#endif
//set here to open your trace code. //WB
-u32 rt_global_debug_component =
- // COMP_INIT |
- // COMP_EPROM |
- // COMP_PHY |
- // COMP_RF |
-// COMP_FIRMWARE |
- // COMP_TRACE |
- // COMP_DOWN |
- // COMP_SWBW |
- // COMP_SEC |
-// COMP_QOS |
-// COMP_RATE |
- // COMP_RECV |
- // COMP_SEND |
- // COMP_POWER |
- // COMP_EVENTS |
- // COMP_RESET |
- // COMP_CMDPKT |
- // COMP_POWER_TRACKING |
- // COMP_INTR |
- COMP_ERR ; //always open err flags on
+u32 rt_global_debug_component = COMP_ERR ; //always open err flags on
static DEFINE_PCI_DEVICE_TABLE(rtl8192_pci_id_tbl) = {
-#ifdef RTL8190P
- /* Realtek */
- /* Dlink */
- { PCI_DEVICE(0x10ec, 0x8190) },
- /* Corega */
- { PCI_DEVICE(0x07aa, 0x0045) },
- { PCI_DEVICE(0x07aa, 0x0046) },
-#else
/* Realtek */
{ PCI_DEVICE(0x10ec, 0x8192) },
/* Corega */
{ PCI_DEVICE(0x07aa, 0x0044) },
{ PCI_DEVICE(0x07aa, 0x0047) },
-#endif
{}
};
void CamResetAllEntry(struct net_device *dev)
{
- write_nic_dword(dev, RWCAM, BIT31|BIT30);
+ struct r8192_priv* priv = ieee80211_priv(dev);
+ write_nic_dword(priv, RWCAM, BIT31|BIT30);
}
-
-void write_cam(struct net_device *dev, u8 addr, u32 data)
+void write_cam(struct r8192_priv *priv, u8 addr, u32 data)
{
- write_nic_dword(dev, WCAMI, data);
- write_nic_dword(dev, RWCAM, BIT31|BIT16|(addr&0xff) );
+ write_nic_dword(priv, WCAMI, data);
+ write_nic_dword(priv, RWCAM, BIT31|BIT16|(addr&0xff) );
}
-u32 read_cam(struct net_device *dev, u8 addr)
+
+u32 read_cam(struct r8192_priv *priv, u8 addr)
{
- write_nic_dword(dev, RWCAM, 0x80000000|(addr&0xff) );
- return read_nic_dword(dev, 0xa8);
+ write_nic_dword(priv, RWCAM, 0x80000000|(addr&0xff) );
+ return read_nic_dword(priv, 0xa8);
}
#ifdef CONFIG_RTL8180_IO_MAP
-u8 read_nic_byte(struct net_device *dev, int x)
+u8 read_nic_byte(struct r8192_priv *priv, int x)
{
+ struct net_device *dev = priv->ieee80211->dev;
return 0xff&inb(dev->base_addr +x);
}
-u32 read_nic_dword(struct net_device *dev, int x)
+u32 read_nic_dword(struct r8192_priv *priv, int x)
{
+ struct net_device *dev = priv->ieee80211->dev;
return inl(dev->base_addr +x);
}
-u16 read_nic_word(struct net_device *dev, int x)
+u16 read_nic_word(struct r8192_priv *priv, int x)
{
+ struct net_device *dev = priv->ieee80211->dev;
return inw(dev->base_addr +x);
}
-void write_nic_byte(struct net_device *dev, int x,u8 y)
+void write_nic_byte(struct r8192_priv *priv, int x,u8 y)
{
+ struct net_device *dev = priv->ieee80211->dev;
outb(y&0xff,dev->base_addr +x);
}
-void write_nic_word(struct net_device *dev, int x,u16 y)
+void write_nic_word(struct r8192_priv *priv, int x,u16 y)
{
+ struct net_device *dev = priv->ieee80211->dev;
outw(y,dev->base_addr +x);
}
-void write_nic_dword(struct net_device *dev, int x,u32 y)
+void write_nic_dword(struct r8192_priv *priv, int x,u32 y)
{
+ struct net_device *dev = priv->ieee80211->dev;
outl(y,dev->base_addr +x);
}
#else /* RTL_IO_MAP */
-u8 read_nic_byte(struct net_device *dev, int x)
+u8 read_nic_byte(struct r8192_priv *priv, int x)
{
+ struct net_device *dev = priv->ieee80211->dev;
return 0xff&readb((u8*)dev->mem_start +x);
}
-u32 read_nic_dword(struct net_device *dev, int x)
+u32 read_nic_dword(struct r8192_priv *priv, int x)
{
+ struct net_device *dev = priv->ieee80211->dev;
return readl((u8*)dev->mem_start +x);
}
-u16 read_nic_word(struct net_device *dev, int x)
+u16 read_nic_word(struct r8192_priv *priv, int x)
{
+ struct net_device *dev = priv->ieee80211->dev;
return readw((u8*)dev->mem_start +x);
}
-void write_nic_byte(struct net_device *dev, int x,u8 y)
+void write_nic_byte(struct r8192_priv *priv, int x,u8 y)
{
+ struct net_device *dev = priv->ieee80211->dev;
writeb(y,(u8*)dev->mem_start +x);
udelay(20);
}
-void write_nic_dword(struct net_device *dev, int x,u32 y)
+void write_nic_dword(struct r8192_priv *priv, int x,u32 y)
{
+ struct net_device *dev = priv->ieee80211->dev;
writel(y,(u8*)dev->mem_start +x);
udelay(20);
}
-void write_nic_word(struct net_device *dev, int x,u16 y)
+void write_nic_word(struct r8192_priv *priv, int x,u16 y)
{
+ struct net_device *dev = priv->ieee80211->dev;
writew(y,(u8*)dev->mem_start +x);
udelay(20);
}
{
case HW_VAR_BSSID:
- write_nic_dword(dev, BSSIDR, ((u32*)(val))[0]);
- write_nic_word(dev, BSSIDR+2, ((u16*)(val+2))[0]);
+ write_nic_dword(priv, BSSIDR, ((u32*)(val))[0]);
+ write_nic_word(priv, BSSIDR+2, ((u16*)(val+2))[0]);
break;
case HW_VAR_MEDIA_STATUS:
{
RT_OP_MODE OpMode = *((RT_OP_MODE *)(val));
- u8 btMsr = read_nic_byte(dev, MSR);
+ u8 btMsr = read_nic_byte(priv, MSR);
btMsr &= 0xfc;
break;
}
- write_nic_byte(dev, MSR, btMsr);
+ write_nic_byte(priv, MSR, btMsr);
}
break;
u32 RegRCR, Type;
Type = ((u8*)(val))[0];
- RegRCR = read_nic_dword(dev,RCR);
+ RegRCR = read_nic_dword(priv, RCR);
priv->ReceiveConfig = RegRCR;
if (Type == true)
else if (Type == false)
RegRCR &= (~RCR_CBSSID);
- write_nic_dword(dev, RCR,RegRCR);
+ write_nic_dword(priv, RCR,RegRCR);
priv->ReceiveConfig = RegRCR;
}
case HW_VAR_SLOT_TIME:
{
priv->slot_time = val[0];
- write_nic_byte(dev, SLOT_TIME, val[0]);
+ write_nic_byte(priv, SLOT_TIME, val[0]);
}
break;
regTmp = priv->basic_rate;
if (priv->short_preamble)
regTmp |= BRSR_AckShortPmb;
- write_nic_dword(dev, RRSR, regTmp);
+ write_nic_dword(priv, RRSR, regTmp);
}
break;
case HW_VAR_CPU_RST:
- write_nic_dword(dev, CPU_GEN, ((u32*)(val))[0]);
+ write_nic_dword(priv, CPU_GEN, ((u32*)(val))[0]);
break;
default:
int *eof, void *data)
{
struct net_device *dev = data;
+ struct r8192_priv *priv = ieee80211_priv(dev);
int len = 0;
int i,n;
int max=0xff;
for(i=0;i<16 && n<=max;i++,n++)
len += snprintf(page + len, count - len,
- "%2x ",read_nic_byte(dev,n));
+ "%2x ",read_nic_byte(priv,n));
}
len += snprintf(page + len, count - len,"\n");
len += snprintf(page + len, count - len,
for(i=0;i<16 && n<=max;i++,n++)
len += snprintf(page + len, count - len,
- "%2x ",read_nic_byte(dev,0x100|n));
+ "%2x ",read_nic_byte(priv,0x100|n));
}
len += snprintf(page + len, count - len,
for(i=0;i<16 && n<=max;i++,n++)
len += snprintf(page + len, count - len,
- "%2x ",read_nic_byte(dev,0x300|n));
+ "%2x ",read_nic_byte(priv,0x300|n));
}
*eof = 1;
{
struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
priv->irq_enabled = 1;
- write_nic_dword(dev,INTA_MASK, priv->irq_mask);
+ write_nic_dword(priv, INTA_MASK, priv->irq_mask);
}
void rtl8192_irq_disable(struct net_device *dev)
{
struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
- write_nic_dword(dev,INTA_MASK,0);
+ write_nic_dword(priv, INTA_MASK, 0);
priv->irq_enabled = 0;
}
struct r8192_priv *priv = ieee80211_priv(dev);
u8 msr;
- msr = read_nic_byte(dev, MSR);
+ msr = read_nic_byte(priv, MSR);
msr &= ~ MSR_LINK_MASK;
/* do not change in link_state != WLAN_LINK_ASSOCIATED.
}else
msr |= (MSR_LINK_NONE<<MSR_LINK_SHIFT);
- write_nic_byte(dev, MSR, msr);
+ write_nic_byte(priv, MSR, msr);
}
void rtl8192_set_chan(struct net_device *dev,short ch)
{
struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
- write_nic_dword(dev, RDQDA,priv->rx_ring_dma);
+ write_nic_dword(priv, RDQDA,priv->rx_ring_dma);
}
/* the TX_DESC_BASE setting is according to the following queue index
u32 i;
for (i = 0; i < MAX_TX_QUEUE_COUNT; i++)
- write_nic_dword(dev, TX_DESC_BASE[i], priv->tx_ring[i].dma);
+ write_nic_dword(priv, TX_DESC_BASE[i], priv->tx_ring[i].dma);
ieee80211_reset_queue(priv->ieee80211);
}
void PHY_SetRtl8192eRfOff(struct net_device* dev)
{
+ struct r8192_priv *priv = ieee80211_priv(dev);
+
//disable RF-Chip A/B
rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x0);
//analog to digital off, for power save
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x0);
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x4, 0x0);
// Analog parameter!!Change bias and Lbus control.
- write_nic_byte(dev, ANAPAR_FOR_8192PciE, 0x07);
+ write_nic_byte(priv, ANAPAR_FOR_8192PciE, 0x07);
}
* disable tx/rx. In 8185 we write 0x10 (Reset bit),
* but here we make reference to WMAC and wirte 0x0
*/
- write_nic_byte(dev, CMDR, 0);
+ write_nic_byte(priv, CMDR, 0);
}
mdelay(20);
if (!reset) {
mdelay(150);
-#ifdef RTL8192E
priv->bHwRfOffAction = 2;
-#endif
/*
* Call MgntActSet_RF_State instead to
*/
if (!priv->ieee80211->bSupportRemoteWakeUp) {
PHY_SetRtl8192eRfOff(dev);
- ulRegRead = read_nic_dword(dev,CPU_GEN);
+ ulRegRead = read_nic_dword(priv, CPU_GEN);
ulRegRead |= CPU_GEN_SYSTEM_RESET;
- write_nic_dword(dev,CPU_GEN, ulRegRead);
+ write_nic_dword(priv,CPU_GEN, ulRegRead);
} else {
/* for WOL */
- write_nic_dword(dev, WFCRC0, 0xffffffff);
- write_nic_dword(dev, WFCRC1, 0xffffffff);
- write_nic_dword(dev, WFCRC2, 0xffffffff);
+ write_nic_dword(priv, WFCRC0, 0xffffffff);
+ write_nic_dword(priv, WFCRC1, 0xffffffff);
+ write_nic_dword(priv, WFCRC2, 0xffffffff);
/* Write PMR register */
- write_nic_byte(dev, PMR, 0x5);
+ write_nic_byte(priv, PMR, 0x5);
/* Disable tx, enanble rx */
- write_nic_byte(dev, MacBlkCtrl, 0xa);
+ write_nic_byte(priv, MacBlkCtrl, 0xa);
}
}
tmp = priv->basic_rate;
if (priv->short_preamble)
tmp |= BRSR_AckShortPmb;
- write_nic_dword(dev, RRSR, tmp);
+ write_nic_dword(priv, RRSR, tmp);
if (net->mode & (IEEE_G|IEEE_N_24G))
{
else //long slot time
slot_time = NON_SHORT_SLOT_TIME;
priv->slot_time = slot_time;
- write_nic_byte(dev, SLOT_TIME, slot_time);
+ write_nic_byte(priv, SLOT_TIME, slot_time);
}
}
priv->basic_rate = rate_config &= 0x15f;
/* BSSID */
- write_nic_dword(dev, BSSIDR, ((u32 *)net->bssid)[0]);
- write_nic_word(dev, BSSIDR+4, ((u16 *)net->bssid)[2]);
+ write_nic_dword(priv, BSSIDR, ((u32 *)net->bssid)[0]);
+ write_nic_word(priv, BSSIDR+4, ((u16 *)net->bssid)[2]);
if (priv->ieee80211->iw_mode == IW_MODE_ADHOC)
{
- write_nic_word(dev, ATIMWND, 2);
- write_nic_word(dev, BCN_DMATIME, 256);
- write_nic_word(dev, BCN_INTERVAL, net->beacon_interval);
+ write_nic_word(priv, ATIMWND, 2);
+ write_nic_word(priv, BCN_DMATIME, 256);
+ write_nic_word(priv, BCN_INTERVAL, net->beacon_interval);
/*
* BIT15 of BCN_DRV_EARLY_INT will indicate
* whether software beacon or hw beacon is applied.
*/
- write_nic_word(dev, BCN_DRV_EARLY_INT, 10);
- write_nic_byte(dev, BCN_ERR_THRESH, 100);
+ write_nic_word(priv, BCN_DRV_EARLY_INT, 10);
+ write_nic_byte(priv, BCN_ERR_THRESH, 100);
BcnTimeCfg |= (BcnCW<<BCN_TCFG_CW_SHIFT);
/* TODO: BcnIFS may required to be changed on ASIC */
BcnTimeCfg |= BcnIFS<<BCN_TCFG_IFS;
- write_nic_word(dev, BCN_TCFG, BcnTimeCfg);
+ write_nic_word(priv, BCN_TCFG, BcnTimeCfg);
}
}
__skb_queue_tail(&ring->queue, skb);
spin_unlock_irqrestore(&priv->irq_th_lock,flags);
- write_nic_byte(dev, TPPoll, TPPoll_CQ);
+ write_nic_byte(priv, TPPoll, TPPoll_CQ);
return;
}
if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40) {
if (tcb_desc->bPacketBW) {
pTxFwInfo->TxBandwidth = 1;
-#ifdef RTL8190P
- pTxFwInfo->TxSubCarrier = 3;
-#else
/* use duplicated mode */
pTxFwInfo->TxSubCarrier = 0;
-#endif
} else {
pTxFwInfo->TxBandwidth = 0;
pTxFwInfo->TxSubCarrier = priv->nCur40MhzPrimeSC;
pdesc->OWN = 1;
spin_unlock_irqrestore(&priv->irq_th_lock, flags);
dev->trans_start = jiffies;
- write_nic_word(dev, TPPoll, 0x01<<tcb_desc->queue_index);
+ write_nic_word(priv, TPPoll, 0x01<<tcb_desc->queue_index);
return 0;
}
{
struct r8192_priv *priv = ieee80211_priv(dev);
struct ieee80211_device* ieee = priv->ieee80211;
- //write_nic_word(dev, BCN_INTR_ITV, net->beacon_interval);
+ //write_nic_word(priv, BCN_INTR_ITV, net->beacon_interval);
if (ieee->state == IEEE80211_LINKED)
{
rtl8192_net_update(dev);
rtl8192_update_ratr_table(dev);
-#if 1
+
//add this as in pure N mode, wep encryption will use software way, but there is no chance to set this as wep will not set group key in wext. WB.2008.07.08
if ((KEY_TYPE_WEP40 == ieee->pairwise_key_type) || (KEY_TYPE_WEP104 == ieee->pairwise_key_type))
EnableHWSecurityConfig8192(dev);
-#endif
}
else
{
- write_nic_byte(dev, 0x173, 0);
+ write_nic_byte(priv, 0x173, 0);
}
/*update timing params*/
//rtl8192_set_chan(dev, priv->chan);
if (ieee->iw_mode == IW_MODE_INFRA || ieee->iw_mode == IW_MODE_ADHOC)
{
u32 reg = 0;
- reg = read_nic_dword(dev, RCR);
+ reg = read_nic_dword(priv, RCR);
if (priv->ieee80211->state == IEEE80211_LINKED)
priv->ReceiveConfig = reg |= RCR_CBSSID;
else
priv->ReceiveConfig = reg &= ~RCR_CBSSID;
- write_nic_dword(dev, RCR, reg);
+ write_nic_dword(priv, RCR, reg);
}
}
static void rtl8192_qos_activate(struct work_struct * work)
{
struct r8192_priv *priv = container_of(work, struct r8192_priv, qos_activate);
- struct net_device *dev = priv->ieee80211->dev;
struct ieee80211_qos_parameters *qos_parameters = &priv->ieee80211->current_network.qos_data.parameters;
u8 mode = priv->ieee80211->current_network.mode;
u8 u1bAIFS;
(((u32)(qos_parameters->cw_max[i]))<< AC_PARAM_ECW_MAX_OFFSET)|
(((u32)(qos_parameters->cw_min[i]))<< AC_PARAM_ECW_MIN_OFFSET)|
((u32)u1bAIFS << AC_PARAM_AIFS_OFFSET));
- write_nic_dword(dev, WDCAPARA_ADD[i], u4bAcParam);
- //write_nic_dword(dev, WDCAPARA_ADD[i], 0x005e4332);
+ write_nic_dword(priv, WDCAPARA_ADD[i], u4bAcParam);
+ //write_nic_dword(priv, WDCAPARA_ADD[i], 0x005e4332);
}
success:
}else if(!ieee->pHTInfo->bCurTxBW40MHz && ieee->pHTInfo->bCurShortGI20MHz){
ratr_value |= 0x80000000;
}
- write_nic_dword(dev, RATR0+rate_index*4, ratr_value);
- write_nic_byte(dev, UFWP, 1);
+ write_nic_dword(priv, RATR0+rate_index*4, ratr_value);
+ write_nic_byte(priv, UFWP, 1);
}
static bool GetNmodeSupportBySecCfg8190Pci(struct net_device*dev)
priv->rxbuffersize = 9100;//2048;//1024;
priv->rxringcount = MAX_RX_COUNT;//64;
priv->irq_enabled=0;
- priv->card_8192 = NIC_8192E;
priv->rx_skb_complete = 1;
priv->chan = 1; //set to channel 1
priv->RegWirelessMode = WIRELESS_MODE_AUTO;
priv->RegChannelPlan = 0xf;
- priv->nrxAMPDU_size = 0;
- priv->nrxAMPDU_aggr_num = 0;
- priv->last_rxdesc_tsf_high = 0;
- priv->last_rxdesc_tsf_low = 0;
priv->ieee80211->mode = WIRELESS_MODE_AUTO; //SET AUTO
priv->ieee80211->iw_mode = IW_MODE_INFRA;
priv->ieee80211->ieee_up=0;
priv->ieee80211->short_slot = 1;
priv->promisc = (dev->flags & IFF_PROMISC) ? 1:0;
priv->bcck_in_ch14 = false;
- priv->bfsync_processing = false;
priv->CCKPresentAttentuation = 0;
priv->rfa_txpowertrackingindex = 0;
priv->rfc_txpowertrackingindex = 0;
priv->SetRFPowerStateInProgress = false;
priv->ieee80211->PowerSaveControl.bInactivePs = true;
priv->ieee80211->PowerSaveControl.bIPSModeBackup = false;
- //just for debug
- priv->txpower_checkcnt = 0;
- priv->thermal_readback_index =0;
- priv->txpower_tracking_callback_cnt = 0;
- priv->ccktxpower_adjustcnt_ch14 = 0;
- priv->ccktxpower_adjustcnt_not_ch14 = 0;
priv->ieee80211->current_network.beacon_interval = DEFAULT_BEACONINTERVAL;
priv->ieee80211->iw_mode = IW_MODE_INFRA;
{
struct r8192_priv *priv = ieee80211_priv(dev);
-#ifdef PF_SYNCTHREAD
- priv->priv_wq = create_workqueue(DRV_NAME,0);
-#else
priv->priv_wq = create_workqueue(DRV_NAME);
-#endif
#ifdef ENABLE_IPS
INIT_WORK(&priv->ieee80211->ips_leave_wq, (void*)IPSLeave_wq);
u16 curCR = 0;
struct r8192_priv *priv = ieee80211_priv(dev);
RT_TRACE(COMP_INIT, "===========>%s()\n", __FUNCTION__);
- curCR = read_nic_dword(dev, EPROM_CMD);
+ curCR = read_nic_dword(priv, EPROM_CMD);
RT_TRACE(COMP_INIT, "read from Reg Cmd9346CR(%x):%x\n", EPROM_CMD, curCR);
//whether need I consider BIT5?
priv->epromtype = (curCR & EPROM_CMD_9356SEL) ? EPROM_93c56 : EPROM_93c46;
RT_TRACE(COMP_INIT, "<===========%s(), epromtype:%d\n", __FUNCTION__, priv->epromtype);
}
-/*
- * used to swap endian. as ntohl & htonl are not
- * neccessary to swap endian, so use this instead.
- */
-static inline u16 endian_swap(u16* data)
-{
- u16 tmp = *data;
- *data = (tmp >> 8) | (tmp << 8);
- return *data;
-}
-
/*
* Adapter->EEPROMAddressSize should be set before this function call.
* EEPROM address size can be got through GetEEPROMSize8185()
*/
-static void rtl8192_read_eeprom_info(struct net_device* dev)
+static void rtl8192_read_eeprom_info(struct r8192_priv *priv)
{
- struct r8192_priv *priv = ieee80211_priv(dev);
-
+ struct net_device *dev = priv->ieee80211->dev;
u8 tempval;
-#ifdef RTL8192E
u8 ICVer8192, ICVer8256;
-#endif
u16 i,usValue, IC_Version;
u16 EEPROMId;
-#ifdef RTL8190P
- u8 offset;
- u8 EepromTxPower[100];
-#endif
u8 bMac_Tmp_Addr[6] = {0x00, 0xe0, 0x4c, 0x00, 0x00, 0x01};
RT_TRACE(COMP_INIT, "====> rtl8192_read_eeprom_info\n");
priv->eeprom_ChannelPlan = usValue&0xff;
IC_Version = ((usValue&0xff00)>>8);
-#ifdef RTL8190P
- priv->card_8192_version = (VERSION_8190)(IC_Version);
-#else
- #ifdef RTL8192E
ICVer8192 = (IC_Version&0xf); //bit0~3; 1:A cut, 2:B cut, 3:C cut...
ICVer8256 = ((IC_Version&0xf0)>>4);//bit4~6, bit7 reserved for other RF chip; 1:A cut, 2:B cut, 3:C cut...
RT_TRACE(COMP_INIT, "\nICVer8192 = 0x%x\n", ICVer8192);
if(ICVer8256 == 0x5) //E-cut
priv->card_8192_version= VERSION_8190_BE;
}
- #endif
-#endif
+
switch(priv->card_8192_version)
{
case VERSION_8190_BD:
RT_TRACE(COMP_INIT, "OFDM 2.4G Tx Power Level, Index %d = 0x%02x\n", i+1, priv->EEPROMTxPowerLevelOFDM24G[i+1]);
}
}
- else if(priv->epromtype== EPROM_93c56)
- {
- #ifdef RTL8190P
- // Read CrystalCap from EEPROM
- if(!priv->AutoloadFailFlag)
- {
- priv->EEPROMAntPwDiff = EEPROM_Default_AntTxPowerDiff;
- priv->EEPROMCrystalCap = (u8)(((eprom_read(dev, (EEPROM_C56_CrystalCap>>1))) & 0xf000)>>12);
- }
- else
- {
- priv->EEPROMAntPwDiff = EEPROM_Default_AntTxPowerDiff;
- priv->EEPROMCrystalCap = EEPROM_Default_TxPwDiff_CrystalCap;
- }
- RT_TRACE(COMP_INIT,"EEPROMAntPwDiff = %d\n", priv->EEPROMAntPwDiff);
- RT_TRACE(COMP_INIT, "EEPROMCrystalCap = %d\n", priv->EEPROMCrystalCap);
-
- // Get Tx Power Level by Channel
- if(!priv->AutoloadFailFlag)
- {
- // Read Tx power of Channel 1 ~ 14 from EEPROM.
- for(i = 0; i < 12; i+=2)
- {
- if (i <6)
- offset = EEPROM_C56_RfA_CCK_Chnl1_TxPwIndex + i;
- else
- offset = EEPROM_C56_RfC_CCK_Chnl1_TxPwIndex + i - 6;
- usValue = eprom_read(dev, (offset>>1));
- *((u16*)(&EepromTxPower[i])) = usValue;
- }
- for(i = 0; i < 12; i++)
- {
- if (i <= 2)
- priv->EEPROMRfACCKChnl1TxPwLevel[i] = EepromTxPower[i];
- else if ((i >=3 )&&(i <= 5))
- priv->EEPROMRfAOfdmChnlTxPwLevel[i-3] = EepromTxPower[i];
- else if ((i >=6 )&&(i <= 8))
- priv->EEPROMRfCCCKChnl1TxPwLevel[i-6] = EepromTxPower[i];
- else
- priv->EEPROMRfCOfdmChnlTxPwLevel[i-9] = EepromTxPower[i];
- }
- }
- else
- {
- priv->EEPROMRfACCKChnl1TxPwLevel[0] = EEPROM_Default_TxPowerLevel;
- priv->EEPROMRfACCKChnl1TxPwLevel[1] = EEPROM_Default_TxPowerLevel;
- priv->EEPROMRfACCKChnl1TxPwLevel[2] = EEPROM_Default_TxPowerLevel;
-
- priv->EEPROMRfAOfdmChnlTxPwLevel[0] = EEPROM_Default_TxPowerLevel;
- priv->EEPROMRfAOfdmChnlTxPwLevel[1] = EEPROM_Default_TxPowerLevel;
- priv->EEPROMRfAOfdmChnlTxPwLevel[2] = EEPROM_Default_TxPowerLevel;
-
- priv->EEPROMRfCCCKChnl1TxPwLevel[0] = EEPROM_Default_TxPowerLevel;
- priv->EEPROMRfCCCKChnl1TxPwLevel[1] = EEPROM_Default_TxPowerLevel;
- priv->EEPROMRfCCCKChnl1TxPwLevel[2] = EEPROM_Default_TxPowerLevel;
-
- priv->EEPROMRfCOfdmChnlTxPwLevel[0] = EEPROM_Default_TxPowerLevel;
- priv->EEPROMRfCOfdmChnlTxPwLevel[1] = EEPROM_Default_TxPowerLevel;
- priv->EEPROMRfCOfdmChnlTxPwLevel[2] = EEPROM_Default_TxPowerLevel;
- }
- RT_TRACE(COMP_INIT, "priv->EEPROMRfACCKChnl1TxPwLevel[0] = 0x%x\n", priv->EEPROMRfACCKChnl1TxPwLevel[0]);
- RT_TRACE(COMP_INIT, "priv->EEPROMRfACCKChnl1TxPwLevel[1] = 0x%x\n", priv->EEPROMRfACCKChnl1TxPwLevel[1]);
- RT_TRACE(COMP_INIT, "priv->EEPROMRfACCKChnl1TxPwLevel[2] = 0x%x\n", priv->EEPROMRfACCKChnl1TxPwLevel[2]);
- RT_TRACE(COMP_INIT, "priv->EEPROMRfAOfdmChnlTxPwLevel[0] = 0x%x\n", priv->EEPROMRfAOfdmChnlTxPwLevel[0]);
- RT_TRACE(COMP_INIT, "priv->EEPROMRfAOfdmChnlTxPwLevel[1] = 0x%x\n", priv->EEPROMRfAOfdmChnlTxPwLevel[1]);
- RT_TRACE(COMP_INIT, "priv->EEPROMRfAOfdmChnlTxPwLevel[2] = 0x%x\n", priv->EEPROMRfAOfdmChnlTxPwLevel[2]);
- RT_TRACE(COMP_INIT, "priv->EEPROMRfCCCKChnl1TxPwLevel[0] = 0x%x\n", priv->EEPROMRfCCCKChnl1TxPwLevel[0]);
- RT_TRACE(COMP_INIT, "priv->EEPROMRfCCCKChnl1TxPwLevel[1] = 0x%x\n", priv->EEPROMRfCCCKChnl1TxPwLevel[1]);
- RT_TRACE(COMP_INIT, "priv->EEPROMRfCCCKChnl1TxPwLevel[2] = 0x%x\n", priv->EEPROMRfCCCKChnl1TxPwLevel[2]);
- RT_TRACE(COMP_INIT, "priv->EEPROMRfCOfdmChnlTxPwLevel[0] = 0x%x\n", priv->EEPROMRfCOfdmChnlTxPwLevel[0]);
- RT_TRACE(COMP_INIT, "priv->EEPROMRfCOfdmChnlTxPwLevel[1] = 0x%x\n", priv->EEPROMRfCOfdmChnlTxPwLevel[1]);
- RT_TRACE(COMP_INIT, "priv->EEPROMRfCOfdmChnlTxPwLevel[2] = 0x%x\n", priv->EEPROMRfCOfdmChnlTxPwLevel[2]);
-#endif
-
- }
//
// Update HAL variables.
//
switch(priv->CustomerID)
{
case RT_CID_DEFAULT:
- #ifdef RTL8190P
- priv->LedStrategy = HW_LED;
- #else
- #ifdef RTL8192E
priv->LedStrategy = SW_LED_MODE1;
- #endif
- #endif
break;
case RT_CID_819x_CAMEO:
//break;
default:
- #ifdef RTL8190P
- priv->LedStrategy = HW_LED;
- #else
- #ifdef RTL8192E
priv->LedStrategy = SW_LED_MODE1;
- #endif
- #endif
break;
}
rtl8192_init_priv_lock(priv);
rtl8192_init_priv_task(dev);
rtl8192_get_eeprom_size(dev);
- rtl8192_read_eeprom_info(dev);
+ rtl8192_read_eeprom_info(priv);
rtl8192_get_channel_map(dev);
init_hal_dm(dev);
init_timer(&priv->watch_dog_timer);
break;
}
- write_nic_byte(dev, BW_OPMODE, regBwOpMode);
+ write_nic_byte(priv, BW_OPMODE, regBwOpMode);
{
u32 ratr_value = 0;
ratr_value = regRATR;
{
ratr_value &= ~(RATE_ALL_OFDM_2SS);
}
- write_nic_dword(dev, RATR0, ratr_value);
- write_nic_byte(dev, UFWP, 1);
+ write_nic_dword(priv, RATR0, ratr_value);
+ write_nic_byte(priv, UFWP, 1);
}
- regTmp = read_nic_byte(dev, 0x313);
+ regTmp = read_nic_byte(priv, 0x313);
regRRSR = ((regTmp) << 24) | (regRRSR & 0x00ffffff);
- write_nic_dword(dev, RRSR, regRRSR);
+ write_nic_dword(priv, RRSR, regRRSR);
//
// Set Retry Limit here
//
- write_nic_word(dev, RETRY_LIMIT,
+ write_nic_word(priv, RETRY_LIMIT,
priv->ShortRetryLimit << RETRY_LIMIT_SHORT_SHIFT |
priv->LongRetryLimit << RETRY_LIMIT_LONG_SHIFT);
// Set Contention Window here
RT_STATUS rtStatus = RT_STATUS_SUCCESS;
//u8 eRFPath;
u8 tmpvalue;
-#ifdef RTL8192E
u8 ICVersion,SwitchingRegulatorOutput;
-#endif
bool bfirmwareok = true;
-#ifdef RTL8190P
- u8 ucRegRead;
-#endif
u32 tmpRegA, tmpRegC, TempCCk;
int i =0;
rtl8192_pci_resetdescring(dev);
// 2007/11/02 MH Before initalizing RF. We can not use FW to do RF-R/W.
priv->Rf_Mode = RF_OP_By_SW_3wire;
-#ifdef RTL8192E
+
//dPLL on
if(priv->ResetProgress == RESET_TYPE_NORESET)
{
- write_nic_byte(dev, ANAPAR, 0x37);
+ write_nic_byte(priv, ANAPAR, 0x37);
// Accordign to designer's explain, LBUS active will never > 10ms. We delay 10ms
// Joseph increae the time to prevent firmware download fail
mdelay(500);
}
-#endif
+
//PlatformSleepUs(10000);
// For any kind of InitializeAdapter process, we shall use system now!!
priv->pFirmware->firmware_status = FW_STATUS_0_INIT;
//3 //Config CPUReset Register
//3//
//3 Firmware Reset Or Not
- ulRegRead = read_nic_dword(dev, CPU_GEN);
+ ulRegRead = read_nic_dword(priv, CPU_GEN);
if(priv->pFirmware->firmware_status == FW_STATUS_0_INIT)
{ //called from MPInitialized. do nothing
ulRegRead |= CPU_GEN_SYSTEM_RESET;
else
RT_TRACE(COMP_ERR, "ERROR in %s(): undefined firmware state(%d)\n", __FUNCTION__, priv->pFirmware->firmware_status);
-#ifdef RTL8190P
- //2008.06.03, for WOL 90 hw bug
- ulRegRead &= (~(CPU_GEN_GPIO_UART));
-#endif
-
- write_nic_dword(dev, CPU_GEN, ulRegRead);
+ write_nic_dword(priv, CPU_GEN, ulRegRead);
//mdelay(100);
-#ifdef RTL8192E
-
//3//
//3 //Fix the issue of E-cut high temperature issue
//3//
// TODO: E cut only
- ICVersion = read_nic_byte(dev, IC_VERRSION);
+ ICVersion = read_nic_byte(priv, IC_VERRSION);
if(ICVersion >= 0x4) //E-cut only
{
// HW SD suggest that we should not wirte this register too often, so driver
// should readback this register. This register will be modified only when
// power on reset
- SwitchingRegulatorOutput = read_nic_byte(dev, SWREGULATOR);
+ SwitchingRegulatorOutput = read_nic_byte(priv, SWREGULATOR);
if(SwitchingRegulatorOutput != 0xb8)
{
- write_nic_byte(dev, SWREGULATOR, 0xa8);
+ write_nic_byte(priv, SWREGULATOR, 0xa8);
mdelay(1);
- write_nic_byte(dev, SWREGULATOR, 0xb8);
+ write_nic_byte(priv, SWREGULATOR, 0xb8);
}
}
-#endif
-
//3//
//3// Initialize BB before MAC
//priv->LoopbackMode = RTL819X_MAC_LOOPBACK;
if(priv->ResetProgress == RESET_TYPE_NORESET)
{
- ulRegRead = read_nic_dword(dev, CPU_GEN);
+ ulRegRead = read_nic_dword(priv, CPU_GEN);
if(priv->LoopbackMode == RTL819X_NO_LOOPBACK)
{
ulRegRead = ((ulRegRead & CPU_GEN_NO_LOOPBACK_MSK) | CPU_GEN_NO_LOOPBACK_SET);
//2008.06.03, for WOL
//ulRegRead &= (~(CPU_GEN_GPIO_UART));
- write_nic_dword(dev, CPU_GEN, ulRegRead);
+ write_nic_dword(priv, CPU_GEN, ulRegRead);
// 2006.11.29. After reset cpu, we sholud wait for a second, otherwise, it may fail to write registers. Emily
udelay(500);
//2=======================================================
// If there is changes, please make sure it applies to all of the FPGA version
//3 Turn on Tx/Rx
- write_nic_byte(dev, CMDR, CR_RE|CR_TE);
+ write_nic_byte(priv, CMDR, CR_RE|CR_TE);
//2Set Tx dma burst
-#ifdef RTL8190P
- write_nic_byte(dev, PCIF, ((MXDMA2_NoLimit<<MXDMA2_RX_SHIFT) |
- (MXDMA2_NoLimit<<MXDMA2_TX_SHIFT) |
- (1<<MULRW_SHIFT)));
-#else
- #ifdef RTL8192E
- write_nic_byte(dev, PCIF, ((MXDMA2_NoLimit<<MXDMA2_RX_SHIFT) |
+ write_nic_byte(priv, PCIF, ((MXDMA2_NoLimit<<MXDMA2_RX_SHIFT) |
(MXDMA2_NoLimit<<MXDMA2_TX_SHIFT) ));
- #endif
-#endif
+
//set IDR0 here
- write_nic_dword(dev, MAC0, ((u32*)dev->dev_addr)[0]);
- write_nic_word(dev, MAC4, ((u16*)(dev->dev_addr + 4))[0]);
+ write_nic_dword(priv, MAC0, ((u32*)dev->dev_addr)[0]);
+ write_nic_word(priv, MAC4, ((u16*)(dev->dev_addr + 4))[0]);
//set RCR
- write_nic_dword(dev, RCR, priv->ReceiveConfig);
+ write_nic_dword(priv, RCR, priv->ReceiveConfig);
//3 Initialize Number of Reserved Pages in Firmware Queue
#ifdef TO_DO_LIST
else
#endif
{
- write_nic_dword(dev, RQPN1, NUM_OF_PAGE_IN_FW_QUEUE_BK << RSVD_FW_QUEUE_PAGE_BK_SHIFT |
+ write_nic_dword(priv, RQPN1, NUM_OF_PAGE_IN_FW_QUEUE_BK << RSVD_FW_QUEUE_PAGE_BK_SHIFT |
NUM_OF_PAGE_IN_FW_QUEUE_BE << RSVD_FW_QUEUE_PAGE_BE_SHIFT |
NUM_OF_PAGE_IN_FW_QUEUE_VI << RSVD_FW_QUEUE_PAGE_VI_SHIFT |
NUM_OF_PAGE_IN_FW_QUEUE_VO <<RSVD_FW_QUEUE_PAGE_VO_SHIFT);
- write_nic_dword(dev, RQPN2, NUM_OF_PAGE_IN_FW_QUEUE_MGNT << RSVD_FW_QUEUE_PAGE_MGNT_SHIFT);
- write_nic_dword(dev, RQPN3, APPLIED_RESERVED_QUEUE_IN_FW|
+ write_nic_dword(priv, RQPN2, NUM_OF_PAGE_IN_FW_QUEUE_MGNT << RSVD_FW_QUEUE_PAGE_MGNT_SHIFT);
+ write_nic_dword(priv, RQPN3, APPLIED_RESERVED_QUEUE_IN_FW|
NUM_OF_PAGE_IN_FW_QUEUE_BCN<<RSVD_FW_QUEUE_PAGE_BCN_SHIFT|
NUM_OF_PAGE_IN_FW_QUEUE_PUB<<RSVD_FW_QUEUE_PAGE_PUB_SHIFT);
}
//3Set Response Rate Setting Register
// CCK rate is supported by default.
// CCK rate will be filtered out only when associated AP does not support it.
- ulRegRead = (0xFFF00000 & read_nic_dword(dev, RRSR)) | RATE_ALL_OFDM_AG | RATE_ALL_CCK;
- write_nic_dword(dev, RRSR, ulRegRead);
- write_nic_dword(dev, RATR0+4*7, (RATE_ALL_OFDM_AG | RATE_ALL_CCK));
+ ulRegRead = (0xFFF00000 & read_nic_dword(priv, RRSR)) | RATE_ALL_OFDM_AG | RATE_ALL_CCK;
+ write_nic_dword(priv, RRSR, ulRegRead);
+ write_nic_dword(priv, RATR0+4*7, (RATE_ALL_OFDM_AG | RATE_ALL_CCK));
//2Set AckTimeout
// TODO: (it value is only for FPGA version). need to be changed!!2006.12.18, by Emily
- write_nic_byte(dev, ACK_TIMEOUT, 0x30);
+ write_nic_byte(priv, ACK_TIMEOUT, 0x30);
//rtl8192_actset_wirelessmode(dev,priv->RegWirelessMode);
if(priv->ResetProgress == RESET_TYPE_NORESET)
SECR_value |= SCR_TxEncEnable;
SECR_value |= SCR_RxDecEnable;
SECR_value |= SCR_NoSKMC;
- write_nic_byte(dev, SECR, SECR_value);
+ write_nic_byte(priv, SECR, SECR_value);
}
//3Beacon related
- write_nic_word(dev, ATIMWND, 2);
- write_nic_word(dev, BCN_INTERVAL, 100);
+ write_nic_word(priv, ATIMWND, 2);
+ write_nic_word(priv, BCN_INTERVAL, 100);
for (i=0; i<QOS_QUEUE_NUM; i++)
- write_nic_dword(dev, WDCAPARA_ADD[i], 0x005e4332);
+ write_nic_dword(priv, WDCAPARA_ADD[i], 0x005e4332);
//
// Switching regulator controller: This is set temporarily.
// It's not sure if this can be removed in the future.
// PJ advised to leave it by default.
//
- write_nic_byte(dev, 0xbe, 0xc0);
+ write_nic_byte(priv, 0xbe, 0xc0);
//2=======================================================
// Set PHY related configuration defined in MAC register bank
}
//if D or C cut
- tmpvalue = read_nic_byte(dev, IC_VERRSION);
+ tmpvalue = read_nic_byte(priv, IC_VERRSION);
priv->IC_Cut = tmpvalue;
RT_TRACE(COMP_INIT, "priv->IC_Cut = 0x%x\n", priv->IC_Cut);
if(priv->IC_Cut >= IC_VersionCut_D)
RT_TRACE(COMP_INIT, "Before C-cut\n");
}
-#if 1
//Firmware download
RT_TRACE(COMP_INIT, "Load Firmware!\n");
bfirmwareok = init_firmware(dev);
return rtStatus;
}
RT_TRACE(COMP_INIT, "Load Firmware finished!\n");
-#endif
+
//RF config
if(priv->ResetProgress == RESET_TYPE_NORESET)
{
rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn, 0x1);
rtl8192_setBBreg(dev, rFPGA0_RFMOD, bOFDMEn, 0x1);
-#ifdef RTL8192E
//Enable Led
- write_nic_byte(dev, 0x87, 0x0);
-#endif
-#ifdef RTL8190P
- //2008.06.03, for WOL
- ucRegRead = read_nic_byte(dev, GPE);
- ucRegRead |= BIT0;
- write_nic_byte(dev, GPE, ucRegRead);
-
- ucRegRead = read_nic_byte(dev, GPO);
- ucRegRead &= ~BIT0;
- write_nic_byte(dev, GPO, ucRegRead);
-#endif
+ write_nic_byte(priv, 0x87, 0x0);
//2=======================================================
// RF Power Save
}
}
#endif
- if(1){
-#ifdef RTL8192E
- // We can force firmware to do RF-R/W
- if(priv->ieee80211->FwRWRF)
- priv->Rf_Mode = RF_OP_By_FW;
- else
- priv->Rf_Mode = RF_OP_By_SW_3wire;
-#else
- priv->Rf_Mode = RF_OP_By_SW_3wire;
-#endif
- }
-#ifdef RTL8190P
- if(priv->ResetProgress == RESET_TYPE_NORESET)
- {
- dm_initialize_txpower_tracking(dev);
-
- tmpRegA= rtl8192_QueryBBReg(dev,rOFDM0_XATxIQImbalance,bMaskDWord);
- tmpRegC= rtl8192_QueryBBReg(dev,rOFDM0_XCTxIQImbalance,bMaskDWord);
-
- if(priv->rf_type == RF_2T4R){
- for(i = 0; i<TxBBGainTableLength; i++)
- {
- if(tmpRegA == priv->txbbgain_table[i].txbbgain_value)
- {
- priv->rfa_txpowertrackingindex= (u8)i;
- priv->rfa_txpowertrackingindex_real= (u8)i;
- priv->rfa_txpowertracking_default = priv->rfa_txpowertrackingindex;
- break;
- }
- }
- }
- for(i = 0; i<TxBBGainTableLength; i++)
- {
- if(tmpRegC == priv->txbbgain_table[i].txbbgain_value)
- {
- priv->rfc_txpowertrackingindex= (u8)i;
- priv->rfc_txpowertrackingindex_real= (u8)i;
- priv->rfc_txpowertracking_default = priv->rfc_txpowertrackingindex;
- break;
- }
- }
- TempCCk = rtl8192_QueryBBReg(dev, rCCK0_TxFilter1, bMaskByte2);
+ // We can force firmware to do RF-R/W
+ if(priv->ieee80211->FwRWRF)
+ priv->Rf_Mode = RF_OP_By_FW;
+ else
+ priv->Rf_Mode = RF_OP_By_SW_3wire;
- for(i=0 ; i<CCKTxBBGainTableLength ; i++)
- {
- if(TempCCk == priv->cck_txbbgain_table[i].ccktxbb_valuearray[0])
- {
- priv->CCKPresentAttentuation_20Mdefault =(u8) i;
- break;
- }
- }
- priv->CCKPresentAttentuation_40Mdefault = 0;
- priv->CCKPresentAttentuation_difference = 0;
- priv->CCKPresentAttentuation = priv->CCKPresentAttentuation_20Mdefault;
- RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex_initial = %d\n", priv->rfa_txpowertrackingindex);
- RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex_real__initial = %d\n", priv->rfa_txpowertrackingindex_real);
- RT_TRACE(COMP_POWER_TRACKING, "priv->rfc_txpowertrackingindex_initial = %d\n", priv->rfc_txpowertrackingindex);
- RT_TRACE(COMP_POWER_TRACKING, "priv->rfc_txpowertrackingindex_real_initial = %d\n", priv->rfc_txpowertrackingindex_real);
- RT_TRACE(COMP_POWER_TRACKING, "priv->CCKPresentAttentuation_difference_initial = %d\n", priv->CCKPresentAttentuation_difference);
- RT_TRACE(COMP_POWER_TRACKING, "priv->CCKPresentAttentuation_initial = %d\n", priv->CCKPresentAttentuation);
- }
-#else
- #ifdef RTL8192E
if(priv->ResetProgress == RESET_TYPE_NORESET)
{
dm_initialize_txpower_tracking(dev);
priv->btxpower_tracking = FALSE;//TEMPLY DISABLE
}
}
- #endif
-#endif
+
rtl8192_irq_enable(dev);
priv->being_init_adapter = false;
return rtStatus;
//rtl8192_beacon_tx_enable(dev);
/* ATIM window */
- write_nic_word(dev, ATIMWND, 2);
+ write_nic_word(priv, ATIMWND, 2);
/* Beacon interval (in unit of TU) */
- write_nic_word(dev, BCN_INTERVAL, net->beacon_interval);
+ write_nic_word(priv, BCN_INTERVAL, net->beacon_interval);
/*
* DrvErlyInt (in unit of TU).
* (Time to send interrupt to notify driver to c
* hange beacon content)
* */
- write_nic_word(dev, BCN_DRV_EARLY_INT, 10);
+ write_nic_word(priv, BCN_DRV_EARLY_INT, 10);
/*
* BcnDMATIM(in unit of us).
* Indicates the time before TBTT to perform beacon queue DMA
* */
- write_nic_word(dev, BCN_DMATIME, 256);
+ write_nic_word(priv, BCN_DMATIME, 256);
/*
* Force beacon frame transmission even after receiving
* beacon frame from other ad hoc STA
* */
- write_nic_byte(dev, BCN_ERR_THRESH, 100);
+ write_nic_byte(priv, BCN_ERR_THRESH, 100);
/* Set CW and IFS */
BcnTimeCfg |= BcnCW<<BCN_TCFG_CW_SHIFT;
BcnTimeCfg |= BcnIFS<<BCN_TCFG_IFS;
- write_nic_word(dev, BCN_TCFG, BcnTimeCfg);
+ write_nic_word(priv, BCN_TCFG, BcnTimeCfg);
/* enable the interrupt for ad-hoc process */
static bool HalTxCheckStuck8190Pci(struct net_device *dev)
{
- u16 RegTxCounter = read_nic_word(dev, 0x128);
struct r8192_priv *priv = ieee80211_priv(dev);
+ u16 RegTxCounter = read_nic_word(priv, 0x128);
bool bStuck = FALSE;
RT_TRACE(COMP_RESET,"%s():RegTxCounter is %d,TxCounter is %d\n",__FUNCTION__,RegTxCounter,priv->TxCounter);
if(priv->TxCounter==RegTxCounter)
break;
}
-#if 1
if(bCheckFwTxCnt)
{
if(HalTxCheckStuck8190Pci(dev))
return RESET_TYPE_SILENT;
}
}
-#endif
+
return RESET_TYPE_NORESET;
}
static bool HalRxCheckStuck8190Pci(struct net_device *dev)
{
struct r8192_priv *priv = ieee80211_priv(dev);
- u16 RegRxCounter = read_nic_word(dev, 0x130);
+ u16 RegRxCounter = read_nic_word(priv, 0x130);
bool bStuck = FALSE;
- static u8 rx_chk_cnt = 0;
+
RT_TRACE(COMP_RESET,"%s(): RegRxCounter is %d,RxCounter is %d\n",__FUNCTION__,RegRxCounter,priv->RxCounter);
// If rssi is small, we should check rx for long time because of bad rx.
// or maybe it will continuous silent reset every 2 seconds.
- rx_chk_cnt++;
+ priv->rx_chk_cnt++;
if(priv->undecorated_smoothed_pwdb >= (RateAdaptiveTH_High+5))
{
- rx_chk_cnt = 0; //high rssi, check rx stuck right now.
+ priv->rx_chk_cnt = 0; /* high rssi, check rx stuck right now. */
}
else if(priv->undecorated_smoothed_pwdb < (RateAdaptiveTH_High+5) &&
((priv->CurrentChannelBW!=HT_CHANNEL_WIDTH_20&&priv->undecorated_smoothed_pwdb>=RateAdaptiveTH_Low_40M) ||
(priv->CurrentChannelBW==HT_CHANNEL_WIDTH_20&&priv->undecorated_smoothed_pwdb>=RateAdaptiveTH_Low_20M)) )
{
- if(rx_chk_cnt < 2)
+ if(priv->rx_chk_cnt < 2)
{
return bStuck;
}
else
{
- rx_chk_cnt = 0;
+ priv->rx_chk_cnt = 0;
}
}
else if(((priv->CurrentChannelBW!=HT_CHANNEL_WIDTH_20&&priv->undecorated_smoothed_pwdb<RateAdaptiveTH_Low_40M) ||
(priv->CurrentChannelBW==HT_CHANNEL_WIDTH_20&&priv->undecorated_smoothed_pwdb<RateAdaptiveTH_Low_20M)) &&
priv->undecorated_smoothed_pwdb >= VeryLowRSSI)
{
- if(rx_chk_cnt < 4)
+ if(priv->rx_chk_cnt < 4)
{
return bStuck;
}
else
{
- rx_chk_cnt = 0;
+ priv->rx_chk_cnt = 0;
}
}
else
{
- if(rx_chk_cnt < 8)
+ if(priv->rx_chk_cnt < 8)
{
return bStuck;
}
else
{
- rx_chk_cnt = 0;
+ priv->rx_chk_cnt = 0;
}
}
if(priv->RxCounter==RegRxCounter)
rfState = priv->ieee80211->eRFPowerState;
TxResetType = TxCheckStuck(dev);
-#if 1
+
if( rfState != eRfOff &&
/*ADAPTER_TEST_STATUS_FLAG(Adapter, ADAPTER_STATUS_FW_DOWNLOAD_FAILURE)) &&*/
(priv->ieee80211->iw_mode != IW_MODE_ADHOC))
// set, STA cannot hear any packet a all. Emily, 2008.04.12
RxResetType = RxCheckStuck(dev);
}
-#endif
RT_TRACE(COMP_RESET,"%s(): TxResetType is %d, RxResetType is %d\n",__FUNCTION__,TxResetType,RxResetType);
if(TxResetType==RESET_TYPE_NORMAL || RxResetType==RESET_TYPE_NORMAL)
// Set the variable for reset.
priv->ResetProgress = RESET_TYPE_SILENT;
// rtl8192_close(dev);
-#if 1
+
down(&priv->wx_sem);
if(priv->up == 0)
{
RT_TRACE(COMP_ERR," ERR!!! %s(): Reset Failed!!\n",__FUNCTION__);
}
}
-#endif
ieee->is_silent_reset = 1;
-#if 1
EnableHWSecurityConfig8192(dev);
-#if 1
if(ieee->state == IEEE80211_LINKED && ieee->iw_mode == IW_MODE_INFRA)
{
ieee->set_chan(ieee->dev, ieee->current_network.channel);
-#if 1
queue_work(ieee->wq, &ieee->associate_complete_wq);
-#endif
}
else if(ieee->state == IEEE80211_LINKED && ieee->iw_mode == IW_MODE_ADHOC)
ieee->data_hard_resume(ieee->dev);
netif_carrier_on(ieee->dev);
}
-#endif
CamRestoreAllEntry(dev);
priv->bResetInProgress = false;
// For test --> force write UFWP.
- write_nic_byte(dev, UFWP, 1);
+ write_nic_byte(priv, UFWP, 1);
RT_TRACE(COMP_RESET, "Reset finished!! ====>[%d]\n", priv->reset_count);
-#endif
}
}
struct net_device *dev = priv->ieee80211->dev;
struct ieee80211_device* ieee = priv->ieee80211;
RESET_TYPE ResetType = RESET_TYPE_NORESET;
- static u8 check_reset_cnt=0;
unsigned long flags;
bool bBusyTraffic = false;
- static u8 last_time = 0;
bool bEnterPS = false;
if ((!priv->up) || priv->bHwRadioOff)
}
//check if reset the driver
spin_lock_irqsave(&priv->tx_lock,flags);
- if(check_reset_cnt++ >= 3 && !ieee->is_roaming && (last_time != 1))
+ if (priv->watchdog_check_reset_cnt++ >= 3 && !ieee->is_roaming &&
+ priv->watchdog_last_time != 1)
{
ResetType = rtl819x_ifcheck_resetornot(dev);
- check_reset_cnt = 3;
+ priv->watchdog_check_reset_cnt = 3;
}
spin_unlock_irqrestore(&priv->tx_lock,flags);
if(!priv->bDisableNormalResetCheck && ResetType == RESET_TYPE_NORMAL)
return;
}
/* disable silent reset temply 2008.9.11*/
-#if 1
+
if( ((priv->force_reset) || (!priv->bDisableNormalResetCheck && ResetType==RESET_TYPE_SILENT))) // This is control by OID set in Pomelo
{
- last_time = 1;
+ priv->watchdog_last_time = 1;
rtl819x_ifsilentreset(dev);
}
else
- last_time = 0;
-#endif
+ priv->watchdog_last_time = 0;
+
priv->force_reset = false;
priv->bForcedSilentReset = false;
priv->bResetInProgress = false;
return -1;
}
RT_TRACE(COMP_INIT, "start adapter finished\n");
-#ifdef RTL8192E
+
if(priv->ieee80211->eRFPowerState!=eRfOn)
MgntActSet_RF_State(dev, eRfOn, priv->ieee80211->RfOffReason);
-#endif
+
if(priv->ieee80211->state != IEEE80211_LINKED)
ieee80211_softmac_start_protocol(priv->ieee80211);
ieee80211_reset_queue(priv->ieee80211);
static void r8192_set_multicast(struct net_device *dev)
{
struct r8192_priv *priv = ieee80211_priv(dev);
- short promisc;
-
- //down(&priv->wx_sem);
-
- /* FIXME FIXME */
-
- promisc = (dev->flags & IFF_PROMISC) ? 1:0;
- if (promisc != priv->promisc) {
- ;
- // rtl8192_commit(dev);
- }
-
- priv->promisc = promisc;
-
- //schedule_work(&priv->reset_wq);
- //up(&priv->wx_sem);
+ priv->promisc = (dev->flags & IFF_PROMISC) ? 1 : 0;
}
setKey(dev, ipw->u.crypt.idx, ipw->u.crypt.idx, ieee->pairwise_key_type, (u8*)ieee->ap_mac_addr, 0, key);
}
if ((ieee->pairwise_key_type == KEY_TYPE_CCMP) && ieee->pHTInfo->bCurrentHTSupport){
- write_nic_byte(dev, 0x173, 1); //fix aes bug
+ write_nic_byte(priv, 0x173, 1); //fix aes bug
}
}
return signal_power;
}
-static void
-rtl8190_process_cck_rxpathsel(
- struct r8192_priv * priv,
- struct ieee80211_rx_stats * pprevious_stats
- )
-{
-#ifdef RTL8190P //Only 90P 2T4R need to check
- char last_cck_adc_pwdb[4]={0,0,0,0};
- u8 i;
-//cosa add for Rx path selection
- if(priv->rf_type == RF_2T4R && DM_RxPathSelTable.Enable)
- {
- if(pprevious_stats->bIsCCK &&
- (pprevious_stats->bPacketToSelf ||pprevious_stats->bPacketBeacon))
- {
- /* record the cck adc_pwdb to the sliding window. */
- if(priv->stats.cck_adc_pwdb.TotalNum++ >= PHY_RSSI_SLID_WIN_MAX)
- {
- priv->stats.cck_adc_pwdb.TotalNum = PHY_RSSI_SLID_WIN_MAX;
- for(i=RF90_PATH_A; i<RF90_PATH_MAX; i++)
- {
- last_cck_adc_pwdb[i] = priv->stats.cck_adc_pwdb.elements[i][priv->stats.cck_adc_pwdb.index];
- priv->stats.cck_adc_pwdb.TotalVal[i] -= last_cck_adc_pwdb[i];
- }
- }
- for(i=RF90_PATH_A; i<RF90_PATH_MAX; i++)
- {
- priv->stats.cck_adc_pwdb.TotalVal[i] += pprevious_stats->cck_adc_pwdb[i];
- priv->stats.cck_adc_pwdb.elements[i][priv->stats.cck_adc_pwdb.index] = pprevious_stats->cck_adc_pwdb[i];
- }
- priv->stats.cck_adc_pwdb.index++;
- if(priv->stats.cck_adc_pwdb.index >= PHY_RSSI_SLID_WIN_MAX)
- priv->stats.cck_adc_pwdb.index = 0;
-
- for(i=RF90_PATH_A; i<RF90_PATH_MAX; i++)
- {
- DM_RxPathSelTable.cck_pwdb_sta[i] = priv->stats.cck_adc_pwdb.TotalVal[i]/priv->stats.cck_adc_pwdb.TotalNum;
- }
-
- for(i=RF90_PATH_A; i<RF90_PATH_MAX; i++)
- {
- if(pprevious_stats->cck_adc_pwdb[i] > (char)priv->undecorated_smoothed_cck_adc_pwdb[i])
- {
- priv->undecorated_smoothed_cck_adc_pwdb[i] =
- ( (priv->undecorated_smoothed_cck_adc_pwdb[i]*(Rx_Smooth_Factor-1)) +
- (pprevious_stats->cck_adc_pwdb[i])) /(Rx_Smooth_Factor);
- priv->undecorated_smoothed_cck_adc_pwdb[i] = priv->undecorated_smoothed_cck_adc_pwdb[i] + 1;
- }
- else
- {
- priv->undecorated_smoothed_cck_adc_pwdb[i] =
- ( (priv->undecorated_smoothed_cck_adc_pwdb[i]*(Rx_Smooth_Factor-1)) +
- (pprevious_stats->cck_adc_pwdb[i])) /(Rx_Smooth_Factor);
- }
- }
- }
- }
-#endif
-}
-
-
/* 2008/01/22 MH We can not delcare RSSI/EVM total value of sliding window to
be a local static. Otherwise, it may increase when we return from S3/S4. The
value will be kept in memory or disk. We must delcare the value in adapter
if(!bcheck)
return;
- rtl8190_process_cck_rxpathsel(priv,pprevious_stats);
-
// <2> Showed on UI for engineering
// hardware does not provide rssi information for each rf path in CCK
if(!pprevious_stats->bIsCCK && pprevious_stats->bPacketToSelf)
{
priv->undecorated_smoothed_pwdb = pprevious_stats->RxPWDBAll;
}
-#if 1
+
if(pprevious_stats->RxPWDBAll > (u32)priv->undecorated_smoothed_pwdb)
{
priv->undecorated_smoothed_pwdb =
( ((priv->undecorated_smoothed_pwdb)*(Rx_Smooth_Factor-1)) +
(pprevious_stats->RxPWDBAll)) /(Rx_Smooth_Factor);
}
-#else
- //Fixed by Jacken 2008-03-20
- if(pPreviousRfd->Status.RxPWDBAll > (u32)pHalData->UndecoratedSmoothedPWDB)
- {
- pHalData->UndecoratedSmoothedPWDB =
- ( ((pHalData->UndecoratedSmoothedPWDB)* 5) + (pPreviousRfd->Status.RxPWDBAll)) / 6;
- pHalData->UndecoratedSmoothedPWDB = pHalData->UndecoratedSmoothedPWDB + 1;
- }
- else
- {
- pHalData->UndecoratedSmoothedPWDB =
- ( ((pHalData->UndecoratedSmoothedPWDB)* 5) + (pPreviousRfd->Status.RxPWDBAll)) / 6;
- }
-#endif
}
//
u8 is_cck_rate=0;
u8 rf_rx_num = 0;
- /* 2007/07/04 MH For OFDM RSSI. For high power or not. */
- static u8 check_reg824 = 0;
- static u32 reg824_bit9 = 0;
-
is_cck_rate = rx_hal_is_cck_rate(pdrvinfo);
// Record it for next packet processing
pstats->bPacketBeacon = precord_stats->bPacketBeacon = bPacketBeacon;
pstats->bToSelfBA = precord_stats->bToSelfBA = bToSelfBA;
/*2007.08.30 requested by SD3 Jerry */
- if(check_reg824 == 0)
+ if (priv->phy_check_reg824 == 0)
{
- reg824_bit9 = rtl8192_QueryBBReg(priv->ieee80211->dev, rFPGA0_XA_HSSIParameter2, 0x200);
- check_reg824 = 1;
+ priv->phy_reg824_bit9 = rtl8192_QueryBBReg(priv->ieee80211->dev, rFPGA0_XA_HSSIParameter2, 0x200);
+ priv->phy_check_reg824 = 1;
}
// (2)PWDB, Average PWDB cacluated by hardware (for rate adaptive)
//
u8 report;//, cck_agc_rpt;
-#ifdef RTL8190P
- u8 tmp_pwdb;
- char cck_adc_pwdb[4];
-#endif
-#ifdef RTL8190P //Only 90P 2T4R need to check
- if(priv->rf_type == RF_2T4R && DM_RxPathSelTable.Enable && bpacket_match_bssid)
- {
- for(i=RF90_PATH_A; i<RF90_PATH_MAX; i++)
- {
- tmp_pwdb = pcck_buf->adc_pwdb_X[i];
- cck_adc_pwdb[i] = (char)tmp_pwdb;
- cck_adc_pwdb[i] /= 2;
- pstats->cck_adc_pwdb[i] = precord_stats->cck_adc_pwdb[i] = cck_adc_pwdb[i];
- }
- }
-#endif
-
- if(!reg824_bit9)
+ if (!priv->phy_reg824_bit9)
{
report = pcck_buf->cck_agc_rpt & 0xc0;
report = report>>6;
//Fixed by Jacken from Bryant 2008-03-20
//Original value is 106
-#ifdef RTL8190P //Modify by Jacken 2008/03/31
- rx_pwr[i] = ((pofdm_buf->trsw_gain_X[i]&0x3F)*2) - 106;
-#else
rx_pwr[i] = ((pofdm_buf->trsw_gain_X[i]&0x3F)*2) - 110;
-#endif
//Get Rx snr value in DB
tmp_rxsnr = pofdm_buf->rxsnr_X[i];
struct r8192_priv *priv = (struct r8192_priv *)ieee80211_priv(dev);
bool bpacket_match_bssid, bpacket_toself;
bool bPacketBeacon=false, bToSelfBA=false;
- static struct ieee80211_rx_stats previous_stats;
struct ieee80211_hdr_3addr *hdr;
u16 fc,type;
(!compare_ether_addr(priv->ieee80211->current_network.bssid, (fc & IEEE80211_FCTL_TODS)? hdr->addr1 : (fc & IEEE80211_FCTL_FROMDS )? hdr->addr2 : hdr->addr3))
&& (!pstats->bHwError) && (!pstats->bCRC)&& (!pstats->bICV));
bpacket_toself = bpacket_match_bssid & (!compare_ether_addr(praddr, priv->ieee80211->dev->dev_addr));
-#if 1//cosa
+
if(WLAN_FC_GET_FRAMETYPE(fc)== IEEE80211_STYPE_BEACON)
{
bPacketBeacon = true;
bToSelfBA = true;
}
-#endif
-
//
// Process PHY information for previous packet (RSSI/PWDB/EVM)
//
// Because phy information is contained in the last packet of AMPDU only, so driver
// should process phy information of previous packet
- rtl8192_process_phyinfo(priv, tmp_buf,&previous_stats, pstats);
- rtl8192_query_rxphystatus(priv, pstats, pdesc, pdrvinfo, &previous_stats, bpacket_match_bssid,
+ rtl8192_process_phyinfo(priv, tmp_buf, &priv->previous_stats, pstats);
+ rtl8192_query_rxphystatus(priv, pstats, pdesc, pdrvinfo, &priv->previous_stats, bpacket_match_bssid,
bpacket_toself ,bPacketBeacon, bToSelfBA);
- rtl8192_record_rxdesc_forlateruse(pstats, &previous_stats);
+ rtl8192_record_rxdesc_forlateruse(pstats, &priv->previous_stats);
}
};
unsigned int count = priv->rxringcount;
- stats.nic_type = NIC_8192E;
-
while (count--) {
rx_desc_819x_pci *pdesc = &priv->rx_ring[priv->rx_idx];//rx descriptor
struct sk_buff *skb = priv->rx_buf[priv->rx_idx];//rx pkt
stats.bFirstMPDU = (pDrvInfo->PartAggr==1) && (pDrvInfo->FirstAGGR==1);
stats.TimeStampLow = pDrvInfo->TSFL;
- stats.TimeStampHigh = read_nic_dword(dev, TSFR+4);
+ stats.TimeStampHigh = read_nic_dword(priv, TSFR+4);
UpdateRxPktTimeStamp8190(dev, &stats);
{
rtl8192_rx(priv->ieee80211->dev);
/* unmask RDU */
- write_nic_dword(priv->ieee80211->dev, INTA_MASK,read_nic_dword(priv->ieee80211->dev, INTA_MASK) | IMR_RDU);
+ write_nic_dword(priv, INTA_MASK, read_nic_dword(priv, INTA_MASK) | IMR_RDU);
}
static const struct net_device_ops rtl8192_netdev_ops = {
dev->netdev_ops = &rtl8192_netdev_ops;
- //DMESG("Oops: i'm coming\n");
-#if WIRELESS_EXT >= 12
-#if WIRELESS_EXT < 17
- dev->get_wireless_stats = r8192_get_wireless_stats;
-#endif
- dev->wireless_handlers = (struct iw_handler_def *) &r8192_wx_handlers_def;
-#endif
- //dev->get_wireless_stats = r8192_get_wireless_stats;
+ dev->wireless_handlers = &r8192_wx_handlers_def;
dev->type=ARPHRD_ETHER;
- dev->watchdog_timeo = HZ*3; //modified by john, 0805
+ dev->watchdog_timeo = HZ*3;
if (dev_alloc_name(dev, ifname) < 0){
RT_TRACE(COMP_INIT, "Oops: devname already taken! Trying wlan%%d...\n");
goto fail;
}
- netif_carrier_off(dev);
- netif_stop_queue(dev);
-
register_netdev(dev);
RT_TRACE(COMP_INIT, "dev name=======> %s\n",dev->name);
rtl8192_proc_init_one(dev);
cancel_delayed_work(&priv->update_beacon_wq);
cancel_delayed_work(&priv->ieee80211->hw_wakeup_wq);
cancel_delayed_work(&priv->ieee80211->hw_sleep_wq);
-#ifdef RTL8192E
cancel_delayed_work(&priv->gpio_change_rf_wq);
-#endif
cancel_work_sync(&priv->reset_wq);
cancel_work_sync(&priv->qos_activate);
//cancel_work_sync(&priv->SetBWModeWorkItem);
printk(KERN_INFO "\nLinux kernel driver for RTL8192 based WLAN cards\n");
printk(KERN_INFO "Copyright (c) 2007-2008, Realsil Wlan\n");
RT_TRACE(COMP_INIT, "Initializing module");
- RT_TRACE(COMP_INIT, "Wireless extensions version %d", WIRELESS_EXT);
rtl8192_proc_module_init();
if(0!=pci_register_driver(&rtl8192_pci_driver))
{
/* ISR: 4bytes */
- inta = read_nic_dword(dev, ISR); /* & priv->IntrMask; */
- write_nic_dword(dev, ISR, inta); /* reset int situation */
+ inta = read_nic_dword(priv, ISR); /* & priv->IntrMask; */
+ write_nic_dword(priv, ISR, inta); /* reset int situation */
if (!inta) {
/*
RT_TRACE(COMP_INTR, "rx descriptor unavailable!\n");
priv->stats.rxrdu++;
/* reset int situation */
- write_nic_dword(dev, INTA_MASK, read_nic_dword(dev, INTA_MASK) & ~IMR_RDU);
+ write_nic_dword(priv, INTA_MASK, read_nic_dword(priv, INTA_MASK) & ~IMR_RDU);
tasklet_schedule(&priv->irq_rx_tasklet);
}
struct ieee80211_device* ieee = priv->ieee80211;
SECR_value = SCR_TxEncEnable | SCR_RxDecEnable;
-#if 1
+
if (((KEY_TYPE_WEP40 == ieee->pairwise_key_type) || (KEY_TYPE_WEP104 == ieee->pairwise_key_type)) && (priv->ieee80211->auth_mode != 2))
{
SECR_value |= SCR_RxUseDK;
SECR_value |= SCR_TxUseDK;
}
-#endif
-
//add HWSec active enable here.
//default using hwsec. when peer AP is in N mode only and pairwise_key_type is none_aes(which HT_IOT_ACT_PURE_N_MODE indicates it), use software security. when peer AP is in b,g,n mode mixed and pairwise_key_type is none_aes, use g mode hw security. WB on 2008.7.4
ieee->hwsec_active = 1;
RT_TRACE(COMP_SEC,"%s:, hwsec:%d, pairwise_key:%d, SECR_value:%x\n", __FUNCTION__,
ieee->hwsec_active, ieee->pairwise_key_type, SECR_value);
{
- write_nic_byte(dev, SECR, SECR_value);//SECR_value | SCR_UseDK );
+ write_nic_byte(priv, SECR, SECR_value);//SECR_value | SCR_UseDK );
}
}
(u32)(*(MacAddr+1)) << 24|
(u32)usConfig;
- write_nic_dword(dev, WCAMI, TargetContent);
- write_nic_dword(dev, RWCAM, TargetCommand);
+ write_nic_dword(priv, WCAMI, TargetContent);
+ write_nic_dword(priv, RWCAM, TargetCommand);
}
else if(i==1){//MAC
TargetContent = (u32)(*(MacAddr+2)) |
(u32)(*(MacAddr+3)) << 8|
(u32)(*(MacAddr+4)) << 16|
(u32)(*(MacAddr+5)) << 24;
- write_nic_dword(dev, WCAMI, TargetContent);
- write_nic_dword(dev, RWCAM, TargetCommand);
+ write_nic_dword(priv, WCAMI, TargetContent);
+ write_nic_dword(priv, RWCAM, TargetCommand);
}
else { //Key Material
if(KeyContent != NULL)
{
- write_nic_dword(dev, WCAMI, (u32)(*(KeyContent+i-2)) );
- write_nic_dword(dev, RWCAM, TargetCommand);
+ write_nic_dword(priv, WCAMI, (u32)(*(KeyContent+i-2)) );
+ write_nic_dword(priv, RWCAM, TargetCommand);
}
}
}