x86: correct MPX insn w/o base or index encoding in 16-bit mode

[deliverable/binutils-gdb.git] / gas / ChangeLog

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 179ebe789a61d4206aef773423c5c90460e17911..006c1fd1804e55616954ad8fd174afb0f3e6efa6 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,55 @@
+2020-03-06  Jan Beulich  <jbeulich@suse.com>
+
+       * config/tc-i386.c (i386_addressing_mode): For 32-bit
+       addressing for MPX insns without base/index.
+       * testsuite/gas/i386/mpx-16bit.s,
+       * testsuite/gas/i386/mpx-16bit.d: New.
+       * testsuite/gas/i386/i386.exp: Run new test.
+
+2020-03-06  Jan Beulich  <jbeulich@suse.com>
+
+       * testsuite/gas/i386/adx.s, testsuite/gas/i386/cet.s,
+       testsuite/gas/i386/ept.s, testsuite/gas/i386/fsgs.s,
+       testsuite/gas/i386/invpcid.s, testsuite/gas/i386/movdir.s,
+       testsuite/gas/i386/ptwrite.s, testsuite/gas/i386/vmx.s,
+       * testsuite/gas/i386/code16.s: Add CR, DR, and TR access cases
+       as well as a BSWAP one.
+       * testsuite/gas/i386/rdpid.s: Add 16-bit case.
+       * testsuite/gas/i386/sse2-16bit.s: Cover more insns.
+       * testsuite/gas/i386/adx-intel.d, testsuite/gas/i386/adx.d,
+       testsuite/gas/i386/cet-intel.d, testsuite/gas/i386/cet.d,
+       testsuite/gas/i386/code16.d, testsuite/gas/i386/ept-intel.d,
+       testsuite/gas/i386/ept.d, testsuite/gas/i386/fsgs-intel.d,
+       testsuite/gas/i386/fsgs.d, testsuite/gas/i386/invpcid-intel.d,
+       testsuite/gas/i386/invpcid.d, testsuite/gas/i386/movdir-intel.d,
+       testsuite/gas/i386/movdir.d, testsuite/gas/i386/ptwrite-intel.d,
+       testsuite/gas/i386/ptwrite.d, testsuite/gas/i386/rdpid-intel.d,
+       testsuite/gas/i386/rdpid.d, testsuite/gas/i386/sse2-16bit.d,
+       testsuite/gas/i386/vmx.d: Adjust expectations.
+
+2020-03-06  Jan Beulich  <jbeulich@suse.com>
+
+       * config/tc-i386.c (md_assemble): Also exclude tpause and umwait
+       from having their operands swapped.
+       * testsuite/gas/i386/waitpkg.s,
+       testsuite/gas/i386/x86-64-waitpkg.s: Add tpause and umwait
+       3-operand cases as well as testing of 16-bit code generation.
+       * testsuite/gas/i386/waitpkg.d,
+       testsuite/gas/i386/waitpkg-intel.d,
+       testsuite/gas/i386/x86-64-waitpkg.d,
+       testsuite/gas/i386/x86-64-waitpkg-intel.d: Adjust expectations.
+
 2020-03-04  Nelson Chu  <nelson.chu@sifive.com>
 
+       * config/tc-riscv.c (percent_op_utype): Support the modifier
+       %got_pcrel_hi.
+       * doc/c-riscv.texi: Add documentation.
+       * testsuite/gas/riscv/no-relax-reloc.d: Add test case for the new
+       modifier %got_pcrel_hi.
+       * testsuite/gas/riscv/no-relax-reloc.s: Likewise.
+       * testsuite/gas/riscv/relax-reloc.d: Likewise.
+       * testsuite/gas/riscv/relax-reloc.s: Likewise.
+
        * doc/c-riscv.texi (relocation modifiers): Add documentation.
        (RISC-V-Formats): Update the section name from "Instruction Formats"
        to "RISC-V Instruction Formats".