+2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com>
+ Alexander Ivchenko <alexander.ivchenko@intel.com>
+ Maxim Kuznetsov <maxim.kuznetsov@intel.com>
+ Sergey Lega <sergey.s.lega@intel.com>
+ Anna Tikhonova <anna.tikhonova@intel.com>
+ Ilya Tocar <ilya.tocar@intel.com>
+ Andrey Turetskiy <andrey.turetskiy@intel.com>
+ Ilya Verbin <ilya.verbin@intel.com>
+ Kirill Yukhin <kirill.yukhin@intel.com>
+ Michael Zolotukhin <michael.v.zolotukhin@intel.com>
+
+ * config/tc-i386-intel.c (O_zmmword_ptr): New.
+ (i386_types): Add zmmword.
+ (i386_intel_simplify_register): Allow regzmm.
+ (i386_intel_simplify): Handle zmmwords.
+ (i386_intel_operand): Handle RC/SAE, vector operations and
+ zmmwords.
+ * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New.
+ (struct RC_Operation): New.
+ (struct Mask_Operation): New.
+ (struct Broadcast_Operation): New.
+ (vex_prefix): Size of bytes increased to 4 to support EVEX
+ encoding.
+ (enum i386_error): Add new error codes: unsupported_broadcast,
+ broadcast_not_on_src_operand, broadcast_needed,
+ unsupported_masking, mask_not_on_destination, no_default_mask,
+ unsupported_rc_sae, rc_sae_operand_not_last_imm,
+ invalid_register_operand, try_vector_disp8.
+ (struct _i386_insn): Add new fields vrex, need_vrex, mask,
+ rounding, broadcast, memshift.
+ (struct RC_name): New.
+ (RC_NamesTable): New.
+ (evexlig): New.
+ (evexwig): New.
+ (extra_symbol_chars): Add '{'.
+ (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF.
+ (i386_operand_type): Add regzmm, regmask and vec_disp8.
+ (match_mem_size): Handle zmmwords.
+ (operand_type_match): Handle zmm-registers.
+ (mode_from_disp_size): Handle vec_disp8.
+ (fits_in_vec_disp8): New.
+ (md_begin): Handle {} properly.
+ (type_names): Add "rZMM", "Mask reg" and "Vector d8".
+ (build_vex_prefix): Handle vrex.
+ (build_evex_prefix): New.
+ (process_immext): Adjust to properly handle EVEX.
+ (md_assemble): Add EVEX encoding support.
+ (swap_2_operands): Correctly handle operands with masking,
+ broadcasting or RC/SAE.
+ (check_VecOperands): Support EVEX features.
+ (VEX_check_operands): Properly handle 16 upper [xyz]mm registers.
+ (match_template): Support regzmm and handle new error codes.
+ (process_suffix): Handle zmmwords and zmm-registers.
+ (check_byte_reg): Extend to zmm-registers.
+ (process_operands): Extend to zmm-registers.
+ (build_modrm_byte): Handle EVEX.
+ (output_insn): Adjust to properly handle EVEX case.
+ (disp_size): Handle vec_disp8.
+ (output_disp): Support compressed disp8*N evex feature.
+ (output_imm): Handle RC/SAE immediates properly.
+ (check_VecOperations): New.
+ (i386_immediate): Handle EVEX features.
+ (i386_index_check): Handle zmmwords and zmm-registers.
+ (RC_SAE_immediate): New.
+ (i386_att_operand): Handle EVEX features.
+ (parse_real_register): Add a check for ZMM/Mask registers.
+ (OPTION_MEVEXLIG): New.
+ (OPTION_MEVEXWIG): New.
+ (md_longopts): Add mevexlig and mevexwig.
+ (md_parse_option): Handle mevexlig and mevexwig options.
+ (md_show_usage): Add description for mevexlig and mevexwig.
+ * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd,
+ avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig.
+
+2013-07-25 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
+
+ * config/tc-i386.c (cpu_arch): Add .sha.
+ * doc/c-i386.texi: Document sha/.sha.
+
+2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
+ Kirill Yukhin <kirill.yukhin@intel.com>
+ Michael Zolotukhin <michael.v.zolotukhin@intel.com>
+
+ * config/tc-i386.c (BND_PREFIX): New.
+ (struct _i386_insn): Add new field bnd_prefix.
+ (add_bnd_prefix): New.
+ (cpu_arch): Add MPX.
+ (i386_operand_type): Add regbnd.
+ (md_assemble): Handle BND prefixes.
+ (parse_insn): Likewise.
+ (output_branch): Likewise.
+ (output_jump): Likewise.
+ (build_modrm_byte): Handle regbnd.
+ (OPTION_MADD_BND_PREFIX): New.
+ (md_longopts): Add entry for 'madd-bnd-prefix'.
+ (md_parse_option): Handle madd-bnd-prefix option.
+ (md_show_usage): Add description for madd-bnd-prefix
+ option.
+ * doc/c-i386.texi: Document mpx/.mpx and -madd-bnd-prefix.
+
+2013-07-24 Tristan Gingold <gingold@adacore.com>
+
+ * config/tc-ppc.c (md_apply_fix): Adjust BFD_RELOC_PPC_B16 on
+ xcoff targets.
+
+2013-07-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
+
+ * config/tc-s390.c (s390_machine): Don't force the .machine
+ argument to lower case.
+
+2013-07-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
+
+ * config/tc-arm.c (s_arm_arch_extension): Improve error message
+ for invalid extension.
+
+2013-07-19 Yufeng Zhang <yufeng.zhang@arm.com>
+
+ * config/tc-aarch64.c (enum aarch64_abi_type): New enumeration tag.
+ (AARCH64_ABI_LP64, AARCH64_ABI_ILP32): New enumerators.
+ (aarch64_abi): New variable.
+ (ilp32_p): Change to be a macro.
+ (aarch64_opts): Remove the support for option -milp32 and -mlp64.
+ (struct aarch64_option_abi_value_table): New struct.
+ (aarch64_abis): New table.
+ (aarch64_parse_abi): New function.
+ (aarch64_long_opts): Add entry for -mabi=.
+ * doc/as.texinfo (Target AArch64 options): Document -mabi.
+ * doc/c-aarch64.texi: Likewise.
+
+2013-07-18 Jim Thomas <thomas@cfht.hawaii.edu>
+
+ * config/tc-i386-intel.c (i386_intel_operand): Fixed signed vs
+ unsigned comparison.
+
+2013-07-18 Sandeep Kumar Singh <Sandeep.Singh2@kpitcummins.com>
+
+ * config/rx-defs.h: Add macros for RX100, RX200, RX600, and
+ RX610.
+ * config/rx-parse.y: (rx_check_float_support): Add function to
+ check floating point operation support for target RX100 and
+ RX200.
+ * config/tc-rx.c: Add CPU options RX100, RX200, RX600, and RX610.
+ * doc/c-rx.texi: Add -mcpu option to recognize macros for RX100,
+ RX200, RX600, and RX610
+
+2013-07-18 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
+
+ * config/tc-avr.c (md_show_usage): Add avrxmega2 to help text
+
+2013-07-18 Vishnu K.S <vishnu.k_s@atmel.com>
+
+ * config/tc-avr.c: Make ata6289's ISA to AVR_ISA_AVR4.
+ * doc/c-avr.texi: Likewise.
+
+2013-07-15 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.c (match_save_restore_list_operand): Avoid -Wformat
+ error with older GCCs.
+ (mips16_macro_build): Dereference args.
+
+2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.c (mips_prefer_vec_regno, mips_parse_register):
+ New functions, split out from...
+ (reg_lookup): ...here. Remove itbl support.
+ (reglist_lookup): Delete.
+ (mips_operand_token_type): New enum.
+ (mips_operand_token): New structure.
+ (mips_operand_tokens): New variable.
+ (mips_add_token, mips_parse_base_start, mips_parse_argument_token)
+ (mips_parse_arguments): New functions.
+ (md_begin): Initialize mips_operand_tokens.
+ (mips_arg_info): Add a token field. Remove optional_reg field.
+ (match_char, match_expression): New functions.
+ (match_const_int): Use match_expression. Remove "s" argument
+ and return a boolean result. Remove O_register handling.
+ (match_regno, match_reg, match_reg_range): New functions.
+ (match_int_operand, match_mapped_int_operand, match_msb_operand)
+ (match_reg_operand, match_reg_pair_operand, match_perf_reg_operand)
+ (match_addiusp_operand, match_clo_clz_dest_operand)
+ (match_lwm_swm_list_operand, match_entry_exit_operand)
+ (match_save_restore_list_operand, match_mdmx_imm_reg_operand)
+ (match_tied_reg_operand): Remove "s" argument and return a boolean
+ result. Match tokens rather than text. Update calls to
+ match_const_int. Rely on match_regno to call check_regno.
+ (match_pcrel_operand, match_pc_operand): Replace "s" argument with
+ "arg" argument. Return a boolean result.
+ (parse_float_constant): Replace with...
+ (match_float_constant): ...this new function.
+ (match_operand): Remove "s" argument and return a boolean result.
+ Update calls to subfunctions.
+ (mips_ip, mips16_ip): Call mips_parse_arguments. Use match routines
+ rather than string-parsing routines. Update handling of optional
+ registers for token scheme.
+
+2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.c (parse_float_constant): Split out from...
+ (mips_ip): ...here.
+
+2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.c (INSERT_BITS, INSERT_OPERAND, MIPS16_INSERT_OPERAND):
+ Delete.
+
+2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.c (mips32_to_16_reg_map): Delete.
+ (match_entry_exit_operand): New function.
+ (match_save_restore_list_operand): Likewise.
+ (match_operand): Use them.
+ (check_absolute_expr): Delete.
+ (mips16_ip): Rewrite main parsing loop to use mips_operands.
+
+2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.c: Enable functions commented out in previous patch.
+ (SKIP_SPACE_TABS): Move further up file.
+ (mips32_to_micromips_reg_b_map, mips32_to_micromips_reg_c_map)
+ (mips32_to_micromips_reg_d_map, mips32_to_micromips_reg_e_map)
+ (ips32_to_micromips_reg_f_map, mips32_to_micromips_reg_g_map)
+ (mips32_to_micromips_reg_l_map, mips32_to_micromips_reg_m_map)
+ (mips32_to_micromips_reg_q_map, mips32_to_micromips_reg_n_map)
+ (micromips_imm_b_map, micromips_imm_c_map): Delete.
+ (mips_lookup_reg_pair): Delete.
+ (macro): Use report_bad_range and report_bad_field.
+ (mips_immed, expr_const_in_range): Delete.
+ (mips_ip): Rewrite main parsing loop to use new functions.
+
+2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.c (mips_oddfpreg_ok): Move further up file.
+ Change return type to bfd_boolean.
+ (report_bad_range, report_bad_field): New functions.
+ (mips_arg_info): New structure.
+ (match_const_int, convert_reg_type, check_regno, match_int_operand)
+ (match_mapped_int_operand, match_msb_operand, match_reg_operand)
+ (match_reg_pair_operand, match_pcrel_operand, match_perf_reg_operand)
+ (match_addiusp_operand, match_clo_clz_dest_operand)
+ (match_lwm_swm_list_operand, match_mdmx_imm_reg_operand)
+ (match_pc_operand, match_tied_reg_operand, match_operand)
+ (check_completed_insn): New functions, commented out for now.
+
+2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.c (insn_insert_operand): New function.
+ (macro_build, mips16_macro_build): Put null character check
+ in the for loop and convert continues to breaks. Use operand
+ structures to handle constant operands.
+
+2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.c (validate_mips_insn): Move further up file.
+ Add insn_bits and decode_operand arguments. Use the mips_operand
+ fields to work out which bits an operand occupies. Detect double
+ definitions.
+ (validate_micromips_insn): Move further up file. Call into
+ validate_mips_insn.
+
+2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.c (mips16_macro_build): Remove 'Y' case.
+
+2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.c (macro_build): Take an int for "C", "k", "\\"
+ and "~".
+ (macro): Update accordingly.
+
+2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.c (imm_expr, imm2_expr, offset_expr): Tweak commentary.
+ (imm_reloc): Delete.
+ (md_assemble): Remove imm_reloc handling.
+ (mips_ip): Update commentary. Use offset_expr and offset_reloc
+ rather than imm_expr and imm_reloc for 'i', 'j' and 'u'.
+ Use a temporary array rather than imm_reloc when parsing
+ constant expressions. Remove imm_reloc initialization.
+ (mips16_ip): Update commentary. Use offset_expr and offset_reloc
+ for the relaxable field. Use a relax_char variable to track the
+ type of this field. Remove imm_reloc initialization.
+
+2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.c (mips16_ip): Handle "I".
+
+2013-07-12 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * config/tc-mips.c (mips_flag_nan2008): New variable.
+ (options): Add OPTION_NAN enum value.
+ (md_longopts): Handle it.
+ (md_parse_option): Likewise.
+ (s_nan): New function.
+ (mips_elf_final_processing): Handle EF_MIPS_NAN2008.
+ (md_show_usage): Add -mnan.
+
+ * doc/as.texinfo (Overview): Add -mnan.
+ * doc/c-mips.texi (MIPS Opts): Document -mnan.
+ (MIPS NaN Encodings): New node. Document .nan directive.
+ (MIPS-Dependent): List the new node.
+
+2013-07-09 Tristan Gingold <gingold@adacore.com>
+
+ * configure.com: Define HAVE_SYS_TYPES_H and HAVE_UNISTD_H
+
+2013-07-08 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.c (mips_ip): Unconditionally parse an expression
+ for 'A' and assume that the constant has been elided if the result
+ is an O_register.
+
+2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.c (gprel16_reloc_p): New function.
+ (macro_read_relocs): Assume BFD_RELOC_LO16 if all relocs are
+ BFD_RELOC_UNUSED.
+ (offset_high_part, small_offset_p): New functions.
+ (nacro): Use them. Remove *_OB and *_DOB cases. For single-
+ register load and store macros, handle the 16-bit offset case first.
+ If a 16-bit offset is not suitable for the instruction we're
+ generating, load it into the temporary register using
+ ADDRESS_ADDI_INSN. Make the M_LI_DD code fall through into the
+ M_L_DAB code once the address has been constructed. For double load
+ and store macros, again handle the 16-bit offset case first.
+ If the second register cannot be accessed from the same high
+ part as the first, load it into AT using ADDRESS_ADDI_INSN.
+ Fix the handling of LD in cases where the first register is the
+ same as the base. Also handle the case where the offset is
+ not 16 bits and the second register cannot be accessed from the
+ same high part as the first. For unaligned loads and stores,
+ fuse the offbits == 12 and old "ab" handling. Apply this handling
+ whenever the second offset needs a different high part from the first.
+ Construct the offset using ADDRESS_ADDI_INSN where possible,
+ for offbits == 16 as well as offbits == 12. Use offset_reloc
+ when constructing the individual loads and stores.
+ (mips_ip): Set up imm_expr, imm2_expr, offset_expr, imm_reloc
+ and offset_reloc before matching against a particular opcode.
+ Handle elided 'A' constants. Allow 'A' constants to use
+ relocation operators.
+
+2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.c (validate_mips_insn): Remove "[" and "]" handling.
+ (mips_ip): Likewise. Do not set is_mdmx for INSN_5400 instructions.
+ Check constraints on the VR5400 RZU.OB, SLL.OB and SRL.OB instructions.
+
+2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.c (mips_ip): Preserve the real bit number for "+p".
+ Require the msb to be <= 31 for "+s". Check that the size is <= 31
+ for both "+s" and "+S".
+
+2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.c (validate_mips_insn, validate_micromips_insn):
+ (mips_ip, mips16_ip): Handle "+i".
+
+2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.c (mips32_to_micromips_reg_h_map): Delete.
+ (micromips_to_32_reg_h_map): Rename to...
+ (micromips_to_32_reg_h_map1): ...this.
+ (micromips_to_32_reg_i_map): Rename to...
+ (micromips_to_32_reg_h_map2): ...this.
+ (mips_lookup_reg_pair): New function.
+ (gpr_write_mask, macro): Adjust after above renaming.
+ (validate_micromips_insn): Remove "mi" handling.
+ (mips_ip): Likewise. Parse both registers in a pair for "mh".
+
+2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.c (validate_mips_insn, validate_micromips_insn)
+ (mips_ip): Remove "+D" and "+T" handling.
+
+2013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
+
+ * config/tc-s390.c (md_gather_operands, md_apply_fix): Support new
+ relocs.
+
+2013-07-03 Marcus Shawcroft <marcus.shawcroft@arm.com>
+
+ * config/tc-aarch64.c (reloc_table): Merge got_prel19 into got.
+
+2013-07-02 Marcus Shawcroft <marcus.shawcroft@arm.com>
+
+ * config/tc-aarch64.c (md_apply_fix): Reorder case values.
+ (aarch64_force_relocation): Likewise.
+
+2013-07-02 Alan Modra <amodra@gmail.com>
+
+ * config/tc-ppc.c (ppc_elf_adjust_symtab): Don't make .TOC. weak.
+
+2013-06-26 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * doc/as.texinfo (Overview): Remove @samp from MIPS ISA names.
+ * doc/c-mips.texi (MIPS Options): Remove @sc from MIPS ISA names.
+ Replace @sc{mips16} with literal `MIPS16'.
+ (MIPS ISA): Replace @sc{mips3} with literal `MIPS III'.
+
+2013-06-26 Yufeng Zhang <yufeng.zhang@arm.com>
+
+ * config/tc-aarch64.c (reloc_table): Replace
+ BFD_RELOC_AARCH64_LD64_GOT_LO12_NC with
+ BFD_RELOC_AARCH64_LD_GOT_LO12_NC; likewise to
+ BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC and
+ BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC.
+ (md_apply_fix): Handle BFD_RELOC_AARCH64_LD_GOT_LO12_NC,
+ BFD_RELOC_AARCH64_LD32_GOT_LO12_NC,
+ BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC,
+ BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC,
+ BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC and
+ BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC.
+ (aarch64_force_relocation): Likewise.
+
+2013-06-26 Yufeng Zhang <yufeng.zhang@arm.com>
+
+ * config/tc-aarch64.c (ilp32_p): New static variable.
+ (elf64_aarch64_target_format): Return the target according to the
+ value of 'ilp32_p'.
+ (md_begin): Determine 'mach' according to the value of 'ilp32_p'.
+ (aarch64_opts): Add support for options '-milp32' and '-mlp64'.
+ (aarch64_dwarf2_addr_size): New function.
+ * config/tc-aarch64.h (aarch64_dwarf2_addr_size): New declaration.
+ (DWARF2_ADDR_SIZE): New define.
+
+2013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * doc/c-mips.texi: Use ISA instead of @sc{isa}.
+
+2013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.c (validate_mips_insn): Use STYPE rather than SHAMT.
+
+2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * config/tc-mips.c (mips_set_options): Add insn32 member.
+ (mips_opts): Initialize it.
+ (NOP_INSN, NOP_INSN_SIZE): Handle insn32 mode.
+ (options): Add OPTION_INSN32 and OPTION_NO_INSN32 enum values.
+ (md_longopts): Add "minsn32" and "mno-insn32" options.
+ (is_size_valid): Handle insn32 mode.
+ (md_assemble): Pass instruction string down to macro.
+ (brk_fmt): Add second dimension and insn32 mode initializers.
+ (mfhl_fmt): Likewise.
+ (BRK_FMT, MFHL_FMT): Handle insn32 mode.
+ (macro_build) <'c'>: Handle microMIPS 32-bit BREAK encoding.
+ (macro_build_jalr, move_register): Handle insn32 mode.
+ (macro_build_branch_rs): Likewise.
+ (macro): Handle insn32 mode.
+ <M_JRADDIUSP>, <M_JRC>, <M_MOVEP>: New cases.
+ (mips_ip): Handle insn32 mode.
+ (md_parse_option): Handle OPTION_INSN32 and OPTION_NO_INSN32.
+ (s_mipsset): Handle "insn32" and "noinsn32" pseudo-ops.
+ (mips_handle_align): Handle insn32 mode.
+ (md_show_usage): Add -minsn32 and -mno-insn32.
+
+ * doc/as.texinfo (Target MIPS options): Add -minsn32 and
+ -mno-insn32 options.
+ (-minsn32, -mno-insn32): New options.
+ * doc/c-mips.texi (MIPS Opts): Add -minsn32 and -mno-insn32
+ options.
+ (MIPS assembly options): New node. Document .set insn32 and
+ .set noinsn32.
+ (MIPS-Dependent): List the new node.
+
+2013-06-25 Nick Clifton <nickc@redhat.com>
+
+ * config/tc-msp430.c (msp430_srcoperand): Do not allow the use of
+ the PC in indirect addressing on 430xv2 parts.
+ (msp430_operands): Add version test to hardware bug encoding
+ restrictions.
+
+2013-06-24 Roland McGrath <mcgrathr@google.com>
+
+ * config/tc-arm.c (parse_reg_list): Use skip_past_char for '}',
+ so it skips whitespace before it.
+ (s_arm_unwind_save_mmxwr, s_arm_unwind_save_mmxwcg): Likewise.
+
+ * config/tc-arm.c (arm_symbol_chars): Include '{' and '}'.
+ (arm_reg_parse_multi): Skip whitespace first.
+ (parse_reg_list): Likewise.
+ (parse_vfp_reg_list): Likewise.
+ (s_arm_unwind_save_mmxwcg): Likewise.
+
+2013-06-24 Nick Clifton <nickc@redhat.com>
+
+ PR gas/15623
+ * config/tc-arm.c (do_t_smc): Mark as ending an IT block.
+
+2013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.c (mips_ip): Fix swapped bit numbers in comments.
+
+2013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.c: Assert that offsetT and valueT are at least
+ 8 bytes in size.
+ (GPR_SMIN, GPR_SMAX): New macros.
+ (macro, mips_ip): Remove code for 4-byte valueT and offsetT.
+
+2013-06-22 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.c: Remove OBJ_ELF, OBJ_MAYBE_ELF and IS_ELF
+ conditions. Remove any code deselected by them.
+ (s_mips_frame, s_mips_mask): Handle ECOFF_DEBUGGING case first.
+
+2013-06-22 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * NEWS: Note removal of ECOFF support.
+ * doc/as.texinfo (--emulation): Update for the removal of MIPS ECOFF.
+ * Makefile.am (TARG_ENV_HFILES): Remove config/te-lnews.h.
+ (MULTI_CFILES): Remove config/e-mipsecoff.c.
+ * Makefile.in: Regenerate.
+ * configure.in: Remove MIPS ECOFF references.
+ (mips-sony-bsd*, mips-*-bsd*, mips-*-lnews*-ecoff, mips-*-*-ecoff):
+ Delete cases.
+ (mips-*-irix5*-*, mips*-*-linux*-*, mips*-*-freebsd*)
+ (mips*-*-kfreebsd*-gnu, mips-*-*-elf): Fold into...
+ (mips-*-*): ...this single case.
+ (mipsbecoff, mipslecoff, mipsecoff): Remove emulations. Expect
+ MIPS emulations to be e-mipself*.
+ * configure: Regenerate.
+ * configure.tgt (mips-sony-bsd*, mips-*-ultrix*, mips-*-osf*)
+ (mips-*-ecoff*, mips-*-pe*, mips-*-irix*, ips-*-lnews*, mips-*-riscos*)
+ (mips-*-sysv*): Remove coff and ecoff cases.
+ * as.c (mipsbecoff, mipslecoff, mipsecoff): Remove.
+ * ecoff.c: Remove reference to MIPS ECOFF.
+ * config/e-mipsecoff.c, config/te-lnews.h: Delete files.
+ * config/tc-mips.c (ECOFF_LITTLE_FORMAT): Delete.
+ (RDATA_SECTION_NAME, mips_target_form): Remove COFF and ECOFF cases.
+ (mips_hi_fixup): Tweak comment.
+ (append_insn): Require a howto.
+ (mips_after_parse_args): Remove OBJ_MAYBE_ECOFF code.
+
+2013-06-22 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * doc/as.texinfo: Use MIPS rather than @sc{mips} throughout.
+ Use "CPU" instead of "cpu".
+ * doc/c-mips.texi: Likewise.
+ (MIPS Opts): Rename to MIPS Options.
+ (MIPS option stack): Rename to MIPS Option Stack.
+ (MIPS ASE instruction generation overrides): Rename to
+ MIPS ASE Instruction Generation Overrides (for now).
+ (MIPS floating-point): Rename to MIPS Floating-Point.
+
+2013-06-22 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * doc/c-mips.texi (MIPS Macros): New section.
+ (MIPS Object): Replace with...
+ (MIPS Small Data): ...this new section.
+
+2013-06-22 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * doc/c-mips.texi (MIPS symbol sizes): Move section further up file.
+ Capitalize name. Use @kindex instead of @cindex for .set entries.
+
+2013-06-22 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * doc/c-mips.texi (MIPS Stabs): Remove section.
+
+2013-06-20 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.c (ISA_SUPPORTS_SMARTMIPS, ISA_SUPPORTS_DSP_ASE)
+ (ISA_SUPPORTS_DSP64_ASE, ISA_SUPPORTS_DSPR2_ASE, ISA_SUPPORTS_EVA_ASE)
+ (ISA_SUPPORTS_MT_ASE, ISA_SUPPORTS_MCU_ASE, ISA_SUPPORTS_VIRT_ASE)
+ (ISA_SUPPORTS_VIRT64_ASE): Delete.
+ (mips_ase): New structure.
+ (mips_ases): New table.
+ (FP64_ASES): New macro.
+ (mips_ase_groups): New array.
+ (mips_isa_rev, mips_ase_mask, mips_check_isa_supports_ase)
+ (mips_check_isa_supports_ases, mips_set_ase, mips_lookup_ase): New
+ functions.
+ (is_opcode_valid): Use mips_ases to get the 64-bit ASE flags.
+ (md_parse_option): Use mips_ases and mips_set_ase instead of
+ separate case statements for each ASE option.
+ (mips_after_parse_args): Use FP64_ASES. Use
+ mips_check_isa_supports_ases to check the ASEs against
+ other options.
+ (s_mipsset): Use mips_ases and mips_set_ase instead of
+ separate if statements for each ASE option. Use
+ mips_check_isa_supports_ases, even when a non-ASE option
+ is specified.
+
+2013-06-19 Greta Yorsh <Greta.Yorsh@arm.com>
+
+ * config/tc-arm.c (arm_cpus): Add support for Cortex-A12.
+
+2013-06-18 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.c (md_shortopts, options, md_longopts)
+ (md_longopts_size): Move earlier in file.
+
+2013-06-18 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.c (mips_set_options): Replace separate "ase_*" fields
+ with a single "ase" bitmask.
+ (mips_opts): Update accordingly.
+ (file_ase, file_ase_explicit): New variables.
+ (file_ase_mips3d, file_ase_mdmx, file_ase_smartmips, file_ase_dsp)
+ (file_ase_dspr2, file_ase_eva, file_ase_mt, file_ase_virt): Delete.
+ (ISA_HAS_ROR): Adjust for mips_set_options change.
+ (is_opcode_valid): Take the base ase mask directly from mips_opts.
+ (mips_ip): Adjust for mips_set_options change.
+ (md_parse_option): Likewise. Update file_ase_explicit.
+ (mips_after_parse_args): Adjust for mips_set_options change.
+ Use bitmask operations to select the default ASEs. Set file_ase
+ rather than individual per-ASE variables.
+ (s_mipsset): Adjust for mips_set_options change.
+ (mips_elf_final_processing): Test file_ase rather than
+ file_ase_mdmx. Remove commented-out code.
+
+2013-06-18 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.c (mips_cpu_info): Add an "ase" field.
+ (MIPS_CPU_ASE_SMARTMIPS, MIPS_CPU_ASE_DSP, MIPS_CPU_ASE_MT)
+ (MIPS_CPU_ASE_MIPS3D, MIPS_CPU_ASE_MDMX, MIPS_CPU_ASE_DSPR2)
+ (MIPS_CPU_ASE_MCU, MIPS_CPU_ASE_VIRT, MIPS_CPU_ASE_EVA): Delete.
+ (mips_after_parse_args): Use the new "ase" field to choose
+ the default ASEs.
+ (mips_cpu_info_table): Move ASEs from the "flags" field to the
+ "ase" field.
+
+2013-06-18 Richard Earnshaw <rearnsha@arm.com>
+
+ * config/tc-arm.c (symbol_preemptible): New function.
+ (relax_branch): Use it.
+
+2013-06-17 Catherine Moore <clm@codesourcery.com>
+ Maciej W. Rozycki <macro@codesourcery.com>
+ Chao-Ying Fu <fu@mips.com>
+
+ * config/tc-mips.c (mips_set_options): Add ase_eva.
+ (mips_set_options mips_opts): Add ase_eva.
+ (file_ase_eva): Declare.
+ (ISA_SUPPORTS_EVA_ASE): Define.
+ (IS_SEXT_9BIT_NUM): Define.
+ (MIPS_CPU_ASE_EVA): Define.
+ (is_opcode_valid): Add support for ase_eva.
+ (macro_build): Likewise.
+ (macro): Likewise.
+ (validate_mips_insn): Likewise.
+ (validate_micromips_insn): Likewise.
+ (mips_ip): Likewise.
+ (options): Add OPTION_EVA and OPTION_NO_EVA.
+ (md_longopts): Add -meva and -mno-eva.
+ (md_parse_option): Process new options.
+ (mips_after_parse_args): Check for valid EVA combinations.
+ (s_mipsset): Likewise.
+
+2013-06-14 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
+
+ * dwarf2dbg.h (dwarf2_move_insn): Declare.
+ * dwarf2dbg.c (line_subseg): Add pmove_tail.
+ (get_line_subseg): Add create_p argument. Initialize pmove_tail.
+ (dwarf2_gen_line_info_1): Update call accordingly.
+ (dwarf2_move_insn): New function.
+ * config/tc-mips.c (append_insn): Use dwarf2_move_insn.
+
+2013-06-14 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
+
+ Revert:
+
+ 2011-09-05 Richard Sandiford <rdsandiford@googlemail.com>
+
+ PR gas/13024
+ * dwarf2dbg.c (pending_lines, pending_lines_tail): New variables.
+ (dwarf2_gen_line_info_1): Delete.
+ (dwarf2_push_line, dwarf2_flush_pending_lines): New functions.
+ (dwarf2_gen_line_info, dwarf2_emit_label): Use them.
+ (dwarf2_consume_line_info): Call dwarf2_flush_pending_lines.
+ (dwarf2_directive_loc): Push previous .locs instead of generating
+ them immediately.
+
+2013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
+
+ * config/tc-mips.c (ISA_SUPPORTS_VIRT_ASE): Support micromips.
+ (ISA_SUPPORTS_VIRT64_ASE): Support 64-bit micromips.
+
+2013-06-13 Nick Clifton <nickc@redhat.com>
+
+ PR gas/15602
+ * config/tc-m68k.h (TC_CHECK_ADJUSTED_BROKEN_DOT_WORD): Define.
+ * config/tc-m68k.c (tc_m68k_check_adjusted_broken_word): New
+ function. Generates an error if the adjusted offset is out of a
+ 16-bit range.
+
+2013-06-12 Sandra Loosemore <sandra@codesourcery.com>
+
+ * config/tc-nios2.c (md_apply_fix): Mask constant
+ BFD_RELOC_NIOS2_HIADJ16 value to 16 bits.
+
2013-06-10 Maciej W. Rozycki <macro@codesourcery.com>
* config/tc-mips.c (append_insn): Don't do branch relaxation for
2013-05-28 Yufeng Zhang <yufeng.zhang@arm.com>
* config/tc-aarch64.c (reloc_table): Update to use
- BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21 instead of
+ BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21 instead of
BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE.
(md_apply_fix): Likewise.
(aarch64_force_relocation): Likewise.
projects / deliverable / binutils-gdb.git / blobdiff