+2006-05-04 Alan Modra <amodra@bigpond.net.au>
+
+ * subsegs.h (struct frchain): Delete frch_seg.
+ (frchain_root): Delete.
+ (seg_info): Define as macro.
+ * subsegs.c (frchain_root): Delete.
+ (abs_seg_info, und_seg_info, absolute_frchain): Delete.
+ (subsegs_begin, subseg_change): Adjust for above.
+ (subseg_set_rest): Likewise. Add new frchain structs to seginfo
+ rather than to one big list.
+ (subseg_get): Don't special case abs, und sections.
+ (subseg_new, subseg_force_new): Don't set frchainP here.
+ (seg_info): Delete.
+ (subsegs_print_statistics): Adjust frag chain control list traversal.
+ * debug.c (dmp_frags): Likewise.
+ * dwarf2dbg.c (first_frag_for_seg): Don't start looking for frag
+ at frchain_root. Make use of known frchain ordering.
+ (last_frag_for_seg): Likewise.
+ (get_frag_fix): Likewise. Add seg param.
+ (process_entries, out_debug_aranges): Adjust get_frag_fix calls.
+ * write.c (chain_frchains_together_1): Adjust for struct frchain.
+ (SUB_SEGMENT_ALIGN): Likewise.
+ (subsegs_finish): Adjust frchain list traversal.
+ * config/tc-xtensa.c (xtensa_cleanup_align_frags): Likewise.
+ (xtensa_fix_target_frags, xtensa_mark_narrow_branches): Likewise.
+ (xtensa_mark_zcl_first_insns, xtensa_fix_a0_b_retw_frags): Likewise.
+ (xtensa_fix_b_j_loop_end_frags): Likewise.
+ (xtensa_fix_close_loop_end_frags): Likewise.
+ (xtensa_fix_short_loop_frags, xtensa_sanity_check): Likewise.
+ (retrieve_segment_info): Delete frch_seg initialisation.
+
+2006-05-03 Alan Modra <amodra@bigpond.net.au>
+
+ * subsegs.c (subseg_get): Don't call obj_sec_set_private_data.
+ * config/obj-elf.h (obj_sec_set_private_data): Delete.
+ * config/tc-hppa.c (tc_gen_reloc): Don't use bfd_abs_symbol.
+ * config/tc-mn10300.c (tc_gen_reloc): Likewise.
+
+2006-05-02 Joseph Myers <joseph@codesourcery.com>
+
+ * config/tc-arm.c (do_iwmmxt_wldstbh): Don't multiply offset by 4
+ here.
+ (md_apply_fix3): Multiply offset by 4 here for
+ BFD_RELOC_ARM_CP_OFF_IMM_S2 and BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
+
+2006-05-02 H.J. Lu <hongjiu.lu@intel.com>
+ Jan Beulich <jbeulich@novell.com>
+
+ * config/tc-i386.c (output_invalid_buf): Change size for
+ unsigned char.
+ * config/tc-tic30.c (output_invalid_buf): Likewise.
+
+ * config/tc-i386.c (output_invalid): Cast none-ascii char to
+ unsigned char.
+ * config/tc-tic30.c (output_invalid): Likewise.
+
+2006-05-02 Daniel Jacobowitz <dan@codesourcery.com>
+
+ * doc/Makefile.am (AM_MAKEINFOFLAGS): New.
+ (TEXI2POD): Use AM_MAKEINFOFLAGS.
+ (asconfig.texi): Don't set top_srcdir.
+ * doc/as.texinfo: Don't use top_srcdir.
+ * aclocal.m4, Makefile.in, doc/Makefile.in: Regenerated.
+
+2006-05-02 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (output_invalid_buf): Change size to 16.
+ * config/tc-tic30.c (output_invalid_buf): Likewise.
+
+ * config/tc-i386.c (output_invalid): Use snprintf instead of
+ sprintf.
+ * config/tc-ia64.c (declare_register_set): Likewise.
+ (emit_one_bundle): Likewise.
+ (check_dependencies): Likewise.
+ * config/tc-tic30.c (output_invalid): Likewise.
+
+2006-05-02 Paul Brook <paul@codesourcery.com>
+
+ * config/tc-arm.c (arm_optimize_expr): New function.
+ * config/tc-arm.h (md_optimize_expr): Define
+ (arm_optimize_expr): Add prototype.
+ (TC_FORCE_RELOCATION_SUB_SAME): Define.
+
+2006-05-02 Ben Elliston <bje@au.ibm.com>
+
+ * config/obj-elf.h (ELF_TARGET_SYMBOL_FIELDS): Make single bit
+ field unsigned.
+
+ * sb.h (sb_list_vector): Move to sb.c.
+ * sb.c (free_list): Use type of sb_list_vector directly.
+ (sb_build): Fix off-by-one error in assertion about `size'.
+
+2006-05-01 Ben Elliston <bje@au.ibm.com>
+
+ * listing.c (listing_listing): Remove useless loop.
+ * macro.c (macro_expand): Remove is_positional local variable.
+ * read.c (s_comm_internal): Simplify `if' condition 1 || x -> 1
+ and simplify surrounding expressions, where possible.
+ (assign_symbol): Likewise.
+ (s_weakref): Likewise.
+ * symbols.c (colon): Likewise.
+
+2006-05-01 James Lemke <jwlemke@wasabisystems.com>
+
+ * subsegs.c (subseg_set_rest): Always set seginfp->frchainP if NULL.
+
+2006-04-30 Thiemo Seufer <ths@mips.com>
+ David Ung <davidu@mips.com>
+
+ * config/tc-mips.c (validate_mips_insn): Handling of udi cases.
+ (mips_immed): New table that records various handling of udi
+ instruction patterns.
+ (mips_ip): Adds udi handling.
+
+2006-04-28 Alan Modra <amodra@bigpond.net.au>
+
+ * dwarf2dbg.c (get_line_subseg): Attach new struct line_seg to end
+ of list rather than beginning.
+
+2006-04-26 Julian Brown <julian@codesourcery.com>
+
+ * gas/config/tc-arm.c (neon_is_quarter_float): Move, and rename to...
+ (is_quarter_float): Rename from above. Simplify slightly.
+ (parse_qfloat_immediate): Parse a "quarter precision" floating-point
+ number.
+ (parse_neon_mov): Parse floating-point constants.
+ (neon_qfloat_bits): Fix encoding.
+ (neon_cmode_for_move_imm): Tweak to use floating-point encoding in
+ preference to integer encoding when using the F32 type.
+
+2006-04-26 Julian Brown <julian@codesourcery.com>
+
+ * config/tc-arm.c (neon_el_type): Make NT_invtype be the zero (so
+ zero-initialising structures containing it will lead to invalid types).
+ (arm_it): Add vectype to each operand.
+ (NTA_HASTYPE, NTA_HASINDEX): Constants used in neon_typed_alias
+ defined field.
+ (neon_typed_alias): New structure. Extra information for typed
+ register aliases.
+ (reg_entry): Add neon type info field.
+ (arm_reg_parse): Remove RTYPE argument (revert to previous arguments).
+ Break out alternative syntax for coprocessor registers, etc. into...
+ (arm_reg_alt_syntax): New function. Alternate syntax handling broken
+ out from arm_reg_parse.
+ (parse_neon_type): Move. Return SUCCESS/FAIL.
+ (first_error): New function. Call to ensure first error which occurs is
+ reported.
+ (parse_neon_operand_type): Parse exactly one type.
+ (NEON_ALL_LANES, NEON_INTERLEAVE_LANES): Move.
+ (parse_typed_reg_or_scalar): New function. Handle core of both
+ arm_typed_reg_parse and parse_scalar.
+ (arm_typed_reg_parse): Parse a register with an optional type.
+ (NEON_SCALAR_REG, NEON_SCALAR_INDEX): Extract parts of parse_scalar
+ result.
+ (parse_scalar): Parse a Neon scalar with optional type.
+ (parse_reg_list): Use first_error.
+ (parse_vfp_reg_list): Use arm_typed_reg_parse instead of arm_reg_parse.
+ (neon_alias_types_same): New function. Return true if two (alias) types
+ are the same.
+ (parse_neon_el_struct_list): Use parse_typed_reg_or_scalar. Return type
+ of elements.
+ (insert_reg_alias): Return new reg_entry not void.
+ (insert_neon_reg_alias): New function. Insert type/index information as
+ well as register for alias.
+ (create_neon_reg_alias): New function. Parse .dn/.qn directives and
+ make typed register aliases accordingly.
+ (s_dn, s_qn): New functions. Handle incorrectly used .dn/.qn at start
+ of line.
+ (s_unreq): Delete type information if present.
+ (s_arm_unwind_save_mmxwr): Remove arg 3 from arm_reg_parse calls.
+ (s_arm_unwind_save_mmxwcg): Likewise.
+ (s_arm_unwind_movsp): Likewise.
+ (s_arm_unwind_setfp): Likewise.
+ (parse_shift): Likewise.
+ (parse_shifter_operand): Likewise.
+ (parse_address): Likewise.
+ (parse_tb): Likewise.
+ (tc_arm_regname_to_dw2regnum): Likewise.
+ (md_pseudo_table): Add dn, qn.
+ (parse_neon_mov): Handle typed operands.
+ (parse_operands): Likewise.
+ (neon_type_mask): Add N_SIZ.
+ (N_ALLMODS): New macro.
+ (neon_check_shape): Fix typo in NS_DDD_QQQ case. Use first_error.
+ (el_type_of_type_chk): Add some safeguards.
+ (modify_types_allowed): Fix logic bug.
+ (neon_check_type): Handle operands with types.
+ (neon_three_same): Remove redundant optional arg handling.
+ (do_neon_dyadic_i64_su, do_neon_shl_imm, do_neon_qshl_imm)
+ (do_neon_logic, do_neon_qdmulh, do_neon_fcmp_absolute)
+ (do_neon_step): Adjust accordingly.
+ (neon_cmode_for_logic_imm): Use first_error.
+ (do_neon_bitfield): Call neon_check_type.
+ (neon_dyadic): Rename to...
+ (neon_dyadic_misc): ...this. New name for neon_dyadic. Add bitfield
+ to allow modification of type of the destination.
+ (do_neon_dyadic_if_su, do_neon_dyadic_if_i, do_neon_dyadic_if_i_d)
+ (do_neon_addsub_if_i, do_neon_mul): Adjust accordingly.
+ (do_neon_compare): Make destination be an untyped bitfield.
+ (neon_scalar_for_mul): Use NEON_SCALAR_REG, NEON_SCALAR_INDEX.
+ (neon_mul_mac): Return early in case of errors.
+ (neon_move_immediate): Use first_error.
+ (neon_mac_reg_scalar_long): Fix type to include scalar.
+ (do_neon_dup): Likewise.
+ (do_neon_mov): Likewise (in several places).
+ (do_neon_tbl_tbx): Fix type.
+ (do_neon_ld_st_interleave, neon_alignment_bit, do_neon_ld_st_lane)
+ (do_neon_ld_dup): Exit early in case of errors and/or use
+ first_error.
+ (opcode_lookup): Update for parse_neon_type returning SUCCESS/FAIL.
+ Handle .dn/.qn directives.
+ (REGDEF): Add zero for reg_entry neon field.
+
+2006-04-26 Julian Brown <julian@codesourcery.com>
+
+ * config/tc-arm.c (limits.h): Include.
+ (fpu_arch_vfp_v3, fpu_vfp_ext_v3, fpu_neon_ext_v1)
+ (fpu_vfp_v3_or_neon_ext): Declare constants.
+ (neon_el_type): New enumeration of types for Neon vector elements.
+ (neon_type_el): New struct. Define type and size of a vector element.
+ (NEON_MAX_TYPE_ELS): Define constant. The maximum number of types per
+ instruction.
+ (neon_type): Define struct. The type of an instruction.
+ (arm_it): Add 'vectype' for the current instruction.
+ (isscalar, immisalign, regisimm, isquad): New predicates for operands.
+ (vfp_sp_reg_pos): Rename to...
+ (vfp_reg_pos): ...this, and add VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn
+ tags.
+ (arm_reg_type): Add REG_TYPE_NQ (Neon Q register) and REG_TYPE_NDQ
+ (Neon D or Q register).
+ (reg_expected_msgs): Sync with above. Allow VFD to mean VFP or Neon D
+ register.
+ (GE_OPT_PREFIX_BIG): Define constant, for use in...
+ (my_get_expression): Allow above constant as argument to accept
+ 64-bit constants with optional prefix.
+ (arm_reg_parse): Add extra argument to return the specific type of
+ register in when either a D or Q register (REG_TYPE_NDQ) is
+ requested. Can be NULL.
+ (parse_scalar): New function. Parse Neon scalar (vector reg and index).
+ (parse_reg_list): Update for new arm_reg_parse args.
+ (parse_vfp_reg_list): Allow parsing of Neon D/Q register lists.
+ (parse_neon_el_struct_list): New function. Parse element/structure
+ register lists for VLD<n>/VST<n> instructions.
+ (s_arm_unwind_save_vfp): Update for new parse_vfp_reg_list args.
+ (s_arm_unwind_save_mmxwr): Likewise.
+ (s_arm_unwind_save_mmxwcg): Likewise.
+ (s_arm_unwind_movsp): Likewise.
+ (s_arm_unwind_setfp): Likewise.
+ (parse_big_immediate): New function. Parse an immediate, which may be
+ 64 bits wide. Put results in inst.operands[i].
+ (parse_shift): Update for new arm_reg_parse args.
+ (parse_address): Likewise. Add parsing of alignment specifiers.
+ (parse_neon_mov): Parse the operands of a VMOV instruction.
+ (operand_parse_code): Add OP_RND, OP_RNQ, OP_RNDQ, OP_RNSC, OP_NRDLST,
+ OP_NSTRLST, OP_NILO, OP_RNDQ_I0, OP_RR_RNSC, OP_RNDQ_RNSC, OP_RND_RNSC,
+ OP_VMOV, OP_RNDQ_IMVNb, OP_RNDQ_I63b, OP_I0, OP_I16z, OP_I32z, OP_I64,
+ OP_I64z, OP_oI32b, OP_oRND, OP_oRNQ, OP_oRNDQ.
+ (parse_operands): Handle new codes above.
+ (encode_arm_vfp_sp_reg): Rename to...
+ (encode_arm_vfp_reg): ...this. Handle D regs (0-31) too. Complain if
+ selected VFP version only supports D0-D15.
+ (do_vfp_sp_monadic, do_vfp_sp_dyadic, do_vfp_sp_compare_z)
+ (do_vfp_dp_sp_cvt, do_vfp_reg_from_sp, do_vfp_reg2_from_sp2)
+ (do_vfp_sp_from_reg, do_vfp_sp2_from_reg2, do_vfp_sp_ldst)
+ (do_vfp_dp_ldst, vfp_sp_ldstm, vfp_dp_ldstm): Update for new
+ encode_arm_vfp_reg name, and allow 32 D regs.
+ (do_vfp_dp_rd_rm, do_vfp_dp_rn_rd, do_vfp_dp_rd_rn, do_vfp_dp_rd_rn_rm)
+ (do_vfp_rm_rd_rn): New functions to encode VFP insns allowing 32 D
+ regs.
+ (do_vfp_sp_const, do_vfp_dp_const, vfp_conv, do_vfp_sp_conv_16)
+ (do_vfp_dp_conv_16, do_vfp_sp_conv_32, do_vfp_dp_conv_32): Handle
+ constant-load and conversion insns introduced with VFPv3.
+ (neon_tab_entry): New struct.
+ (NEON_ENC_TAB): Bit patterns for overloaded Neon instructions, and
+ those which are the targets of pseudo-instructions.
+ (neon_opc): Enumerate opcodes, use as indices into...
+ (neon_enc_tab): ...this. Hold data from NEON_ENC_TAB.
+ (NEON_ENC_INTEGER, NEON_ENC_ARMREG, NEON_ENC_POLY, NEON_ENC_FLOAT)
+ (NEON_ENC_SCALAR, NEON_ENC_IMMED, NEON_ENC_INTERLV, NEON_ENC_LANE)
+ (NEON_ENC_DUP): Define meaningful helper macros to look up values in
+ neon_enc_tab.
+ (neon_shape): Enumerate shapes (permitted register widths, etc.) for
+ Neon instructions.
+ (neon_type_mask): New. Compact type representation for type checking.
+ (N_SU_ALL, N_SU_32, N_SU_16_64, N_SUF_32, N_I_ALL, N_IF_32): Common
+ permitted type combinations.
+ (N_IGNORE_TYPE): New macro.
+ (neon_check_shape): New function. Check an instruction shape for
+ multiple alternatives. Return the specific shape for the current
+ instruction.
+ (neon_modify_type_size): New function. Modify a vector type and size,
+ depending on the bit mask in argument 1.
+ (neon_type_promote): New function. Convert a given "key" type (of an
+ operand) into the correct type for a different operand, based on a bit
+ mask.
+ (type_chk_of_el_type): New function. Convert a type and size into the
+ compact representation used for type checking.
+ (el_type_of_type_ckh): New function. Reverse of above (only when a
+ single bit is set in the bit mask).
+ (modify_types_allowed): New function. Alter a mask of allowed types
+ based on a bit mask of modifications.
+ (neon_check_type): New function. Check the type of the current
+ instruction against the variable argument list. The "key" type of the
+ instruction is returned.
+ (neon_dp_fixup): New function. Fill in and modify instruction bits for
+ a Neon data-processing instruction depending on whether we're in ARM
+ mode or Thumb-2 mode.
+ (neon_logbits): New function.
+ (neon_three_same, neon_two_same, do_neon_dyadic_i_su)
+ (do_neon_dyadic_i64_su, neon_imm_shift, do_neon_shl_imm)
+ (do_neon_qshl_imm, neon_cmode_for_logic_imm, neon_bits_same_in_bytes)
+ (neon_squash_bits, neon_is_quarter_float, neon_qfloat_bits)
+ (neon_cmode_for_move_imm, neon_write_immbits, neon_invert_size)
+ (do_neon_logic, do_neon_bitfield, neon_dyadic, do_neon_dyadic_if_su)
+ (do_neon_dyadic_if_su_d, do_neon_dyadic_if_i, do_neon_dyadic_if_i_d)
+ (do_neon_addsub_if_i, neon_exchange_operands, neon_compare)
+ (do_neon_cmp, do_neon_cmp_inv, do_neon_ceq, neon_scalar_for_mul)
+ (neon_mul_mac, do_neon_mac_maybe_scalar, do_neon_tst, do_neon_mul)
+ (do_neon_qdmulh, do_neon_fcmp_absolute, do_neon_fcmp_absolute_inv)
+ (do_neon_step, do_neon_abs_neg, do_neon_sli, do_neon_sri)
+ (do_neon_qshlu_imm, do_neon_qmovn, do_neon_qmovun)
+ (do_neon_rshift_sat_narrow, do_neon_rshift_sat_narrow_u, do_neon_movn)
+ (do_neon_rshift_narrow, do_neon_shll, neon_cvt_flavour, do_neon_cvt)
+ (neon_move_immediate, do_neon_mvn, neon_mixed_length)
+ (do_neon_dyadic_long, do_neon_abal, neon_mac_reg_scalar_long)
+ (do_neon_mac_maybe_scalar_long, do_neon_dyadic_wide, do_neon_vmull)
+ (do_neon_ext, do_neon_rev, do_neon_dup, do_neon_mov)
+ (do_neon_rshift_round_imm, do_neon_movl, do_neon_trn, do_neon_zip_uzp)
+ (do_neon_sat_abs_neg, do_neon_pair_long, do_neon_recip_est)
+ (do_neon_cls, do_neon_clz, do_neon_cnt, do_neon_swp, do_neon_tbl_tbx)
+ (do_neon_ldm_stm, do_neon_ldr_str, do_neon_ld_st_interleave)
+ (neon_alignment_bit, do_neon_ld_st_lane, do_neon_ld_dup)
+ (do_neon_ldx_stx): New functions. Neon bit encoding and encoding
+ helpers.
+ (parse_neon_type): New function. Parse Neon type specifier.
+ (opcode_lookup): Allow parsing of Neon type specifiers.
+ (REGNUM2, REGSETH, REGSET2): New macros.
+ (reg_names): Add new VFPv3 and Neon registers.
+ (NUF, nUF, NCE, nCE): New macros for opcode table.
+ (insns): More VFP registers allowed in fcpyd, fmdhr, fmdlr, fmrdh,
+ fmrdl, fabsd, fnegd, fsqrtd, faddd, fsubd, fmuld, fdivd, fmacd, fmscd,
+ fnmuld, fnmacd, fnmscd, fcmpd, fcmpzd, fcmped, fcmpezd, fmdrr, fmrrd.
+ Add Neon instructions vaba, vhadd, vrhadd, vhsub, vqadd, vqsub, vrshl,
+ vqrshl, vshl, vqshl{u}, vand, vbic, vorr, vorn, veor, vbsl, vbit, vbif,
+ vabd, vmax, vmin, vcge, vcgt, vclt, vcle, vceq, vpmax, vpmin, vmla,
+ vmls, vpadd, vadd, vsub, vtst, vmul, vqdmulh, vqrdmulh, vacge, vacgt,
+ vaclt, vacle, vrecps, vrsqrts, vabs, vneg, v{r}shr, v{r}sra, vsli,
+ vsri, vqshrn, vq{r}shr{u}n, v{r}shrn, vshll, vcvt, vmov, vmvn, vabal,
+ vabdl, vaddl, vsubl, vmlal, vmlsl, vaddw, vsubw, v{r}addhn, v{r}subhn,
+ vqdmlal, vqdmlsl, vqdmull, vmull, vext, vrev64, vrev32, vrev16, vdup,
+ vmovl, v{q}movn, vzip, vuzp, vqabs, vqneg, vpadal, vpaddl, vrecpe,
+ vrsqrte, vcls, vclz, vcnt, vswp, vtrn, vtbl, vtbx, vldm, vstm, vldr,
+ vstr, vld[1234], vst[1234], fconst[sd], f[us][lh]to[sd],
+ fto[us][lh][sd].
+ (tc_arm_regname_to_dw2regnum): Update for arm_reg_parse args.
+ (arm_cpu_option_table): Add Neon and VFPv3 to Cortex-A8.
+ (arm_option_cpu_value): Add vfp3 and neon.
+ (aeabi_set_public_attributes): Support VFPv3 and NEON attributes. Fix
+ VFPv1 attribute.
+
+2006-04-25 Bob Wilson <bob.wilson@acm.org>
+
+ * config/xtensa-relax.c (widen_spec_list): Use new "WIDE.<opcode>"
+ syntax instead of hardcoded opcodes with ".w18" suffixes.
+ (wide_branch_opcode): New.
+ (build_transition): Use it to check for wide branch opcodes with
+ either ".w18" or ".w15" suffixes.
+
+2006-04-25 Bob Wilson <bob.wilson@acm.org>
+
+ * config/tc-xtensa.c (xtensa_create_literal_symbol,
+ xg_assemble_literal, xg_assemble_literal_space): Do not set the
+ frag's is_literal flag.
+
+2006-04-25 Bob Wilson <bob.wilson@acm.org>
+
+ * config/xtensa-relax.c (XCHAL_HAVE_WIDE_BRANCHES): Provide default.
+
+2006-04-23 Kazu Hirata <kazu@codesourcery.com>
+
+ * config/obj-coff.c, config/tc-arm.c, config/tc-bfin.c,
+ config/tc-cris.c, config/tc-crx.c, config/tc-i386.c,
+ config/tc-ia64.c, config/tc-maxq.c, config/tc-maxq.h,
+ config/tc-mips.c, config/tc-msp430.c, config/tc-sh.c,
+ config/tc-tic4x.c, config/tc-xtensa.c: Fix comment typos.
+
2005-04-20 Paul Brook <paul@codesourcery.com>
* config/tc-arm.c (s_arm_arch, s_arm_cpu, s_arm_fpu): Enable for
* config/tc-m68k.c (m68k_cpus): Change cpu_cf5208 entries to use
mcfemac instead of mcfmac.
+2006-03-23 Michael Matz <matz@suse.de>
+
+ * config/tc-i386.c (type_names): Correct placement of 'static'.
+ (reloc): Map some more relocs to their 64 bit counterpart when
+ size is 8.
+ (output_insn): Work around breakage if DEBUG386 is defined.
+ (output_disp): A BFD_RELOC_64 with GOT_symbol as operand also
+ needs to be mapped to BFD_RELOC_X86_64_GOTPC64 or
+ BFD_RELOC_X86_64_GOTPC32. Also x86-64 handles pcrel addressing
+ different from i386.
+ (output_imm): Ditto.
+ (lex_got): Recognize @PLTOFF and @GOTPLT. Make @GOT accept also
+ Imm64.
+ (md_convert_frag): Jumps can now be larger than 2GB away, error
+ out in that case.
+ (tc_gen_reloc): New relocs are passed through. BFD_RELOC_64
+ and BFD_RELOC_64_PCREL are mapped to BFD_RELOC_X86_64_GOTPC64.
+
2006-03-22 Richard Sandiford <richard@codesourcery.com>
Daniel Jacobowitz <dan@codesourcery.com>
Phil Edwards <phil@codesourcery.com>