+2017-12-19 Tamar Christina <tamar.christina@arm.com>
+
+ PR 22529
+ * config/tc-aarch64.c (vectype_to_qualifier): Support AARCH64_OPND_QLF_V_4B.
+ * gas/testsuite/gas/aarch64/pr22529.s: New.
+ * gas/testsuite/gas/aarch64/pr22529.d: New.
+ * gas/testsuite/gas/aarch64/pr22529.l: New.
+
+2017-12-18 Nick Clifton <nickc@redhat.com>
+
+ PR 22493
+ * config/tc-arm.c (encode_ldmstm): Do not use A2 encoding of the
+ PUSH insn when pushing the stack pointer.
+
+2017-12-18 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (regymm, regzmm): Delete.
+ (operand_type_register_match). Extend comment. Also handle some
+ memory operands here. Extend to cover .regsimd.
+ (build_vex_prefix): Derive vector_length from actual operand
+ size.
+ (process_operands, build_modrm_byte): Use .regsimd.
+
+2017-12-18 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (match_simd_size): New.
+ (match_mem_size): Use it.
+ (operand_size_match): Likewise. Split .reg and .acc checks.
+ (pi, check_VecOperands, match_template, check_byte_reg,
+ check_long_reg, check_qword_reg, build_modrm_byte,
+ parse_real_register): Replace .regxmm, .regymm, and .regzmm
+ checks.
+ (md_assemble): Qualify .acc check with .xmmword one.
+ (bad_implicit_operand): Delete.
+ (process_operands): Replace .firstxmm0 checks with .acc plus
+ .xmmword ones. Drop now pointless assertions. Convert .acc to
+ .regsimd.
+ * config/tc-i386-intel.c (i386_intel_simplify_register): Replace
+ .regxmm, .regymm, and .regzmm checks.
+ * testsuite/gas/i386/x86-64-specific-reg.l: Adjust expectations.
+
+2017-12-18 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (operand_type_check): Extend comment.
+ (match_reg_size): Also check .tbyte.
+ (match_mem_size): No longer check .tbyte here.
+ (md_assemble): Drop .floatacc check.
+ (check_byte_reg): Drop .floatreg and .floatacc checks.
+ (process_operands, parse_real_register): Replace .floatreg
+ check.
+
+2017-12-18 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (operand_type_check, pi): Switch .reg<N> to
+ just .reg.
+ (operand_size_match): Qualify .anysize check with .reg one.
+ Extend .acc check to also cover .reg.
+ (operand_type_register_match): Drop m0 and m1 parameters. Switch
+ .reg<N> to .byte/.word/.dword/.qword. Drop .acc special
+ handling.
+ (md_assemble): Expand .reg8 checks to .reg plus .bytes ones.
+ (optimize_imm, process_suffix, check_byte_reg, check_long_reg,
+ check_qword_reg, check_word_reg): Expand .reg<N> checks to .reg
+ plus size ones.
+ (match_template): Drop arguments from calls to
+ operand_type_register_match().
+ (build_modrm_byte, i386_addressing_mode, i386_index_check,
+ parse_real_register): Replace .reg<N> checks.
+ * config/tc-i386-intel.c (i386_intel_simplify,
+ i386_intel_operand): Switch .reg16 to .word.
+
+2017-12-17 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/22623
+ * gas/config/tc-i386.c (output_insn): Check pseudo prefix
+ without instruction.
+ * testsuite/gas/i386/i386.exp: Run inval-pseudo.
+ * testsuite/gas/i386/inval-pseudo.l: New file.
+ * testsuite/gas/i386/inval-pseudo.s: Likewise.
+
+2017-12-15 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (match_template): Add missing ! to
+ reg{x,y,z}mm checks in q- and l-suffix handling.
+
+2017-12-15 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (build_modrm_byte): Add missing ! to reg64
+ check leading to abort().
+
+2017-12-14 Nick Clifton <nickc@redhat.com>
+
+ * config/tc-m32c.c: Update address of FSF in copyright notice.
+ * config/tc-m32c.h: Likewise.
+ * config/tc-mt.c: Likewise.
+ * config/tc-mt.h: Likewise.
+ * config/tc-visium.c: Likewise.
+ * config/tc-visium.h: Likewise.
+ * testsuite/gas/rx/explode: Likewise.
+
+2017-12-13 Jim Wilson <jimw@sifive.com>
+
+ PR 22599
+ * testsuite/gas/riscv/fsxxi.d, testsuite/gas/riscv/fsxxi.s: New.
+
+2017-12-13 Dimitar Dimitrov <dimitar@dinux.eu>
+
+ * testsuite/gas/pru/extern.s: New test for print of U16_PMEMM
+ relocation.
+ * testsuite/gas/pru/extern.d: New test driver.
+
+2017-12-12 Alan Modra <amodra@gmail.com>
+
+ PR 21118
+ * config/tc-ppc.c (md_assemble): Don't mask register number.
+
+2017-12-07 Max Filippov <jcmvbkbc@gmail.com>
+
+ * config/tc-xtensa.c (xg_order_trampoline_chain): Replace
+ xg_order_trampoline_chain_entry call with check for
+ canonicalized symbol equality and offset equality.
+
+2017-12-04 Alan Modra <amodra@gmail.com>
+
+ PR 22544
+ * doc/as.texinfo (8byte): Correct.
+
+2017-12-04 Alan Modra <amodra@gmail.com>
+
+ * testsuite/gas/ppc/ppc.exp: Don't exclude VLE tests when little-endian.
+ * testsuite/gas/ppc/efs.d: Add -mbig to assembler options.
+ * testsuite/gas/ppc/efs2.d: Likewise.
+ * testsuite/gas/ppc/lsp-checks.d: Likewise.
+ * testsuite/gas/ppc/lsp.d: Likewise.
+ * testsuite/gas/ppc/spe.d: Likewise.
+ * testsuite/gas/ppc/spe2-checks.d: Likewise.
+ * testsuite/gas/ppc/spe2.d: Likewise.
+ * testsuite/gas/ppc/spe_ambiguous.d: Likewise.
+ * testsuite/gas/ppc/vle-mult-ld-st-insns.d: Likewise.
+ * testsuite/gas/ppc/vle-reloc.d: Likewise.
+ * testsuite/gas/ppc/vle-simple-1.d: Likewise.
+ * testsuite/gas/ppc/vle-simple-2.d: Likewise.
+ * testsuite/gas/ppc/vle-simple-3.d: Likewise.
+ * testsuite/gas/ppc/vle-simple-4.d: Likewise.
+ * testsuite/gas/ppc/vle-simple-5.d: Likewise.
+ * testsuite/gas/ppc/vle-simple-6.d: Likewise.
+ * testsuite/gas/ppc/vle.d: Likewise.
+
+2017-12-03 Jim Wilson <jimw@sifive.com>
+
+ * doc/c-riscv.texi (RISC-V-Directives): Move @section immediately after
+ @node.
+
+2017-12-01 Palmer Dabbelt <palmer@sifive.com>
+ Jim Wilson <jimw@sifive.com>
+
+ * doc/as.texinfo (RISC-V): Alphabetize RISC-V entries. Change
+ RISC-V-Opts to RISC-V-Options. Delete redundant space. Add -fpic
+ and related options to option list.
+ * doc/c-riscv.texi: (RISC-V-Options): Renamed from RISC-V-Opts.
+ (RISC-V Options): Renamed from Options. Add missing period.
+ (-fpic): Also mention -fPIC.
+ (RISC-V Directives): New node.
+
+2017-12-01 Peter Bergner <bergner@vnet.ibm.com>
+
+ * config/tc-ppc.c (last_insn): Update type.
+ (insn_validate) <omask, mask>: Likewise.
+ (ppc_setup_opcodes) <mask, right_bit>: Likewise.
+ <PRINT_OPCODE_TABLE>: Update types and printf format specifiers.
+ (ppc_insert_operand): Update return and argument types and remove
+ unneeded type casts.
+ <min, max, right, tmp>: Update type.
+ (md_assemble): Remove unneeded type casts.
+ <insn, val, tmp_insn>: Update type.
+
+2017-11-29 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (enum i386_error): Remove try_vector_disp8.
+ (mode_from_disp_size, build_modrm_byte, build_modrm_byte,
+ disp_size): Remove reference to .vec_disp8.
+ (output_disp): Likewise. Unconditionally use i.memshift.
+ (fits_in_vec_disp8): Rename to fits_in_disp8.
+ (type_names): Remove OPERAND_TYPE_VEC_DISP8 entry.
+ (optimize_disp): Use fits_in_disp8.
+ (check_VecOperands): Re-work (simplify) .disp8memshift
+ conditional handling.
+
+2017-11-29 Jan Beulich <jbeulich@suse.com>
+
+ PR gas/21874
+ * config/tc-i386-intel.c (i386_intel_simplify): Chain together
+ multiple segment override expressions.
+ (i386_intel_operand): Issue diagnostic for redundant segment
+ overrides.
+ * testsuite/gas/i386/intelok.e: New.
+ * testsuite/gas/i386/intelok.d: Reference intelok.e.
+ * testsuite/gas/i386/inval-seg.s: Add redundant override checks.
+ * testsuite/gas/i386/inval-seg.l: Adjust expectations.
+
+2017-11-29 Jim Wilson <jimw@sifive.com>
+ Palmer Dabbelt <palmer@sifive.com>
+
+ * config/tc-riscv.c (riscv_frag_align_code): New local insn_alignment.
+ Early return if bytes less than or equal to insn_alignment.
+ * testsuite/gas/riscv/align-1.l: New.
+ * testsuite/gas/riscv/align-1.s: New.
+ * testsuite/gas/riscv/riscv.exp: Use run_dump_tests. Use run_list_test
+ for align-1.
+
+ PR gas/22464
+ * doc/c-i386.texi (-n): Clarify docs.
+
2017-11-29 Renlin Li <renlin.li@arm.com>
* config/tc-aarch64.c (reg_names): Fix IP1 register alias typo.
* testsuite/gas/elf/dwarf2-6.d: Likewise.
* testsuite/gas/elf/dwarf2-7.d: Likewise.
-2017-08-01 H.J. Lu <hongjiu.lu@intel.com>
-
- PR gas/21874
- * config/tc-i386-intel.c (i386_intel_operand): Update segment
- register check.
- * testsuite/gas/i386/intelok.s: Replace "fs:gs:[eax]" with
- "fs:[eax]".
- * testsuite/gas/i386/inval-seg.s: Add tests for invalid segment
- register.
- * testsuite/gas/i386/x86-64-inval-seg.s: Likewise.
- * testsuite/gas/i386/inval-seg.l: Updated.
- * testsuite/gas/i386/x86-64-inval-seg.l: Likewise.
-
2017-07-31 John David Anglin <danglin@gcc.gnu.org>
* config/tc-hppa.c (pa_ip): Clear `d' bit in branch on bit instructions
projects / deliverable / binutils-gdb.git / blobdiff