This is a series of patches that add support for the SPARC M7 cpu to

[deliverable/binutils-gdb.git] / gas / ChangeLog

diff --git a/gas/ChangeLog b/gas/ChangeLog
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+2014-10-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
+
+       * config/tc-sparc.c (v9a_asr_table): Entry for %cps removed.
+       (sparc_arch_table): Remove the HWCAP_RANDOM, HWCAP_TRANS and
+       HWCAP_ASI_CACHE_SPARING from the architectures using them.
+       (HWS_V8): New define.
+       (HWS_V9): Likewise.
+       (HWS_VA): Likewise.
+       (HWS_VB): Likewise.
+       (HWS_VC): Likewise.
+       (HWS_VD): Likewise.
+       (HWS_VE): Likewise.
+       (HWS_VV): Likewise.
+       (sparc_arch): Use the HWS_* macros.  Fix the `sparc4' architecture
+       to cover the HWCAP_ASI_BLK_INIT and HWCAP_IMA capabilities.
+       (hwcap_seen): Variable widened to 64 bits.
+       (hwcap_allowed): Likewise.
+       (sparc_arch): new field `hwcap2_allowed'.
+       (sparc_arch_table): provide hwcap2_allowed values for existing
+       archs.
+       (sparc_md_end): Add a HWCAPS2 object attribute to the elf object
+       in case any of the HWCAP2_* caps are used.
+       (sparc_ip): Take into account the new hwcaps2 bitmap to build the
+       list of seen/allowed hwcaps.
+       (get_hwcap_name): Argument widened to 64 bits to handle HWCAP2
+       bits.
+       (HWS_VM): New define.
+       (HWS2_VM): Likewise.
+       (sparc_arch): New architectures `sparc5', `v9m' and `v8plusm'.
+       (v9a_asr_table): Add the %mwait (%asr28) ancillary state register
+       to the table.
+       (sparc_ip): Handle the %mcdper ancillary state register as an
+       operand.
+       (sparc_ip): Handle } arguments as fdrd floating point registers
+       (double) that are the same than frs1.
+       * doc/c-sparc.texi (Sparc-Opts): Document the -Av9e, -Av8pluse and
+       -xarch=v9e command line options.  Also fix the description of the
+       -Av9v and -Av8plusv command line options.
+       Document the -Av9m, -Av8plusm,-Asparc5, -xarch=v9m and
+       -xarch=sparc5 command line options.
+
+2014-09-29  Terry Guo  <terry.guo@arm.com>
+
+       * as.c (create_obj_attrs_section): Move it and call it from ...
+       * write.c (create_obj_attrs_section): ... here.
+       (subsegs_finish_section): Refactored.
+
+2014-09-27  Alan Modra  <amodra@gmail.com>
+
+       * dwarf2dbg.c (all_segs_hash): Delete.
+       (get_line_subseg): Delete last_seg, last_subseg, last_line_subseg.
+       Retrieve line_seg for section via seg_info.
+       * subsegs.h (segment_info_typet): Add dwarf2_line_seg.
+
+2014-09-23  H.J. Lu  <hongjiu.lu@intel.com>
+
+       PR gas/17421
+       * config/tc-i386.c (md_assemble): Disallow VEX/EVEX encoded
+       instructions in 16-bit mode.
+
+2014-09-22  Alan Modra  <amodra@gmail.com>
+
+       * config/tc-m68k.c (md_assemble): Add assert to work around
+       bogus trunk gcc warning.
+       * config/tc-pj.h (md_convert_frag): Warning fix.
+       * config/tc-xtensa.c (xg_assemble_vliw_tokens): Warning fix.
+
+2014-09-17  Tristan Gingold  <gingold@adacore.com>
+
+       * config/tc-arm.c (move_or_literal_pool, add_to_lit_pool): Use
+       bfd_int64_t instead of int64_t.
+
+2014-09-16  Ilya Tocar  <ilya.tocar@intel.com>
+
+       * config/tc-i386.c (evexrcig): New.
+       (build_evex_prefix): Force rounding bits.
+       (OPTION_MEVEXRCIG): New.
+       (md_longopts): Add mevexrcig.
+       (md_parse_option): Handle OPTION_MEVEXRCIG.
+       (md_show_usage): Document mevexrcig.
+       * doc/c-i386.texi (mevexrcig): Document new option.
+
 2014-09-16  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
 
        * config/tc-nds32.c (nds32_fsrs, nds32_fdrs, nds32_gprs): Remove.