This patch similarly to the AArch64 one enables Dot Product support by default for...
[deliverable/binutils-gdb.git] / gas / ChangeLog
index f095421ee62ea2db7668c210055db799c2767365..6c8482021eb8024cd2f8745d898553dd65783222 100644 (file)
@@ -1,3 +1,222 @@
+2017-11-07  Tamar Christina  <tamar.christina@arm.com>
+
+       * config/tc-arm.c (arm_cpus):
+       Change FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
+       into FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD.
+
+2017-11-07  Alan Modra  <amodra@gmail.com>
+
+       * read.c (assemble_one, s_bundle_unlock): Formatting.
+       Consistently add comma and "bytes" to error message.
+       * testsuite/gas/i386/bundle-bad.l: Adjust to suit.
+
+2017-11-07  Alan Modra  <amodra@gmail.com>
+
+       * testsuite/gas/arm/got_prel.d,
+       * testsuite/gas/elf/dwarf2-1.d,
+       * testsuite/gas/elf/dwarf2-2.d,
+       * testsuite/gas/elf/dwarf2-3.d,
+       * testsuite/gas/elf/dwarf2-5.d,
+       * testsuite/gas/elf/dwarf2-6.d,
+       * testsuite/gas/i386/debug1.d,
+       * testsuite/gas/i386/dw2-compress-1.d,
+       * testsuite/gas/i386/dw2-compress-3a.d,
+       * testsuite/gas/i386/dw2-compress-3b.d,
+       * testsuite/gas/i386/dw2-compressed-1.d,
+       * testsuite/gas/i386/dw2-compressed-3a.d,
+       * testsuite/gas/i386/dw2-compressed-3b.d,
+       * testsuite/gas/i386/ilp32/x86-64-localpic.d,
+       * testsuite/gas/i386/localpic.d,
+       * testsuite/gas/i386/x86-64-localpic.d,
+       * testsuite/gas/ia64/pr13167.d,
+       * testsuite/gas/mips/loc-swap-2.d,
+       * testsuite/gas/mips/loc-swap.d,
+       * testsuite/gas/mips/micromips@loc-swap-2.d,
+       * testsuite/gas/mips/micromips@loc-swap.d,
+       * testsuite/gas/mips/mips16-dwarf2-n32.d,
+       * testsuite/gas/mips/mips16-dwarf2.d,
+       * testsuite/gas/mips/mips16@loc-swap-2.d,
+       * testsuite/gas/mips/mips16@loc-swap.d,
+       * testsuite/gas/mips/mips16e@loc-swap.d,
+       * testsuite/gas/mmix/bspec-1.d,
+       * testsuite/gas/mmix/bspec-2.d,
+       * testsuite/gas/tic6x/unwind-1.d,
+       * testsuite/gas/tic6x/unwind-2.d,
+       * testsuite/gas/tic6x/unwind-3.d: Update for pluralization
+       fixes.
+
+2017-11-07  Alan Modra  <amodra@gmail.com>
+
+       * as.c (main): Properly pluralize messages.
+       * frags.c (frag_grow): Likewise.
+       * read.c (emit_expr_with_reloc, emit_expr_fix): Likewise.
+       (parse_bitfield_cons): Likewise.
+       * write.c (fixup_segment, compress_debug, write_contents): Likewise.
+       (relax_segment): Likewise.
+       * config/tc-arm.c (s_arm_elf_cons): Likewise.
+       * config/tc-cr16.c (l_cons): Likewise.
+       * config/tc-i370.c (i370_elf_cons): Likewise.
+       * config/tc-m68k.c (m68k_elf_cons): Likewise.
+       * config/tc-msp430.c (msp430_operands): Likewise.
+       * config/tc-s390.c (s390_elf_cons, s390_literals): Likewise.
+       * config/tc-mcore.c (md_apply_fix): Likewise.
+       * config/tc-tic54x.c (md_assemble): Likewise.
+       * config/tc-xtensa.c (xtensa_elf_cons): Likewise.
+       (xg_expand_assembly_insn): Likewise.
+       * config/xtensa-relax.c (build_transition): Likewise.
+
+2017-11-07  Alan Modra  <amodra@gmail.com>
+
+       * asintl.h (textdomain, bindtextdomain): Use safer "do nothing".
+       (ngettext, dngettext, dcngettext): Define when !ENABLE_NLS.
+
+2017-11-03  Siddhesh Poyarekar  <siddhesh.poyarekar@linaro.org>
+           Jim Wilson  <jim.wilson@linaro.org>
+
+       * config/tc-aarch64.c (aarch64_cpus): Add saphira.
+       * doc/c-aarch64.texi: Likewise.
+
+2017-11-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
+
+       * testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v6t2-1.d: Add
+       --disassembler-options=force-thumb to objdump options.
+       * testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v6t2-2.d: Likewise.
+
+2017-11-01  James Bowman  <james.bowman@ftdichip.com>
+
+       * config/tc-ft32.c (md_assemble): Add relaxation reloc
+       BFD_RELOC_FT32_RELAX.
+       (md_longopts): Add "norelax" and "no-relax".
+       (md_apply_fix): Add reloc BFD_RELOC_FT32_DIFF32.
+       (relaxable_section, ft32_validate_fix_sub, ft32_force_relocation,
+       ft32_allow_local_subtract): New function.
+       * config/tc-ft32.h: Remove unused MD_PCREL_FROM_SECTION.
+       * testsuite/gas/ft32/insnsc.s: New test exercising all FT32B
+       shortcodes.
+       * testsuite/gas/ft32/insnsc.d: New driver file.
+       * testsuite/gas/all/gas.exp: Update.
+       * testsuite/gas/ft32/ft32.exp: Run the new test.
+       * testsuite/gas/ft32/insn.d: Update.
+       * testsuite/gas/elf/dwarf2-11.d: Update.
+       * testsuite/gas/elf/dwarf2-12.d: Update.
+       * testsuite/gas/elf/dwarf2-13.d: Update.
+       * testsuite/gas/elf/dwarf2-14.d: Update.
+       * testsuite/gas/elf/dwarf2-15.d: Update.
+       * testsuite/gas/elf/dwarf2-16.d: Update.
+       * testsuite/gas/elf/dwarf2-17.d: Update.
+       * testsuite/gas/elf/dwarf2-18.d: Update.
+       * testsuite/gas/elf/dwarf2-3.d: Update.
+       * testsuite/gas/elf/dwarf2-5.d: Update.
+       * testsuite/gas/elf/dwarf2-7.d: Update.
+
+2017-11-01  Thomas Preud'homme  <thomas.preudhomme@arm.com>
+
+       * config/tc-arm.c (arm_ext_v2): Define to ARM_EXT_V2 feature bit.
+       * testsuite/gas/arm/copro.s: Split into
+       * testsuite/gas/arm/copro-arm_v2plus-thumb_v6t2plus.s: This while
+       changing it to unified syntax and
+       * testsuite/gas/arm/copro-arm_v5plus-thumb_v6t2plus.s: this and ...
+       * testsuite/gas/arm/copro-arm_v5teplus-thumb_v6t2plus.s: This and ...
+       * testsuite/gas/arm/copro-arm_v6plus-thumb_v6t2plus.s: This.
+       * testsuite/gas/arm/copro.d: Split into ...
+       * testsuite/gas/arm/copro-arm_v2plus-arm_v2.d: This but target ARMv2
+       and ...
+       * testsuite/gas/arm/copro-arm_v5plus-arm_v5.d: this but target ARMv5
+       and ...
+       * testsuite/gas/arm/copro-arm_v5teplus-arm_v5te.d: This but target
+       ARMv5TE and ...
+       * testsuite/gas/arm/copro-arm_v6plus-arm_v6.d: This but target ARMv6.
+       * testsuite/gas/arm/copro-arm_v2plus-arm_v1.d: New testcase.
+       * testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v4t-1.d: New testcase.
+       * testsuite/gas/arm/copro-arm_v2plus-thumb_v6t2plus-unavail.l: Expected
+       errors for the above two testcases.
+       * testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v6t2-1.d: New testcase.
+       * testsuite/gas/arm/copro-arm_v5plus-arm_v4.d: New testcase.
+       * testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v4t-2.d: New testcase.
+       * testsuite/gas/arm/copro-arm_v5plus-thumb_v6t2plus-unavail.l:
+       Expected errors for the above two testcases.
+       * testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v6t2-2.d: New testcase.
+       * testsuite/gas/arm/copro-arm_v5teplus-arm_v5.d: New testcase.
+       * testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v4t-3.d: New testcase.
+       * testsuite/gas/arm/copro-arm_v5teplus-thumb_v6t2plus-unavail.l:
+       Expected errors for the above two testcases.
+       * testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v6t2-3.d: New testcase.
+       * testsuite/gas/arm/copro-arm_v6plus-arm_v5te.d: New testcase.
+       * testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v4t-4.d: New testcase.
+       * testsuite/gas/arm/copro-arm_v6plus-thumb_v6t2plus-unavail.l:
+       Expected errors for the above two testcases.
+       * testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v6t2-4.d: New testcase.
+
+2017-10-26  H.J. Lu  <hongjiu.lu@intel.com>
+
+       PR gas/22352
+       * config/tc-i386.c (check_VecOperands): Also check XMM register
+       for invalid register in AVX512 gathers.
+       * testsuite/gas/i386/vgather-check.s: Add tests for AVX512
+       gathers with XMM register.
+       * testsuite/gas/i386/x86-64-vgather-check.s: Likewise.
+       * testsuite/gas/i386/vgather-check-error.l: Updated.
+       * testsuite/gas/i386/vgather-check-none.d: Likewise.
+       * testsuite/gas/i386/vgather-check-warn.d: Likewise.
+       * testsuite/gas/i386/vgather-check-warn.e: Likewise.
+       * testsuite/gas/i386/vgather-check.d: Likewise.
+       * testsuite/gas/i386/x86-64-vgather-check-error.l: Likewise.
+       * testsuite/gas/i386/x86-64-vgather-check-none.d: Likewise.
+       * testsuite/gas/i386/x86-64-vgather-check-warn.d: Likewise.
+       * testsuite/gas/i386/x86-64-vgather-check-warn.e: Likewise.
+       * testsuite/gas/i386/x86-64-vgather-check.d: Likewise.
+
+2017-10-26  Hans-Peter Nilsson  <hp@bitrange.com>
+
+       * testsuite/gas/all/fill-1.s: Use L2 rather than .L2.
+
+2017-10-25  Alan Modra  <amodra@gmail.com>
+
+       PR 22348
+       * config/tc-crx.c (instruction, output_opcode): Make static.
+       (relocatable, ins_parse, cur_arg_num): Likewise.
+       (parse_insn): Adjust for renamed opcodes globals.
+       (check_range): Likewise
+
+2017-10-25  Alan Modra  <amodra@gmail.com>
+
+       * testsuite/gas/all/fill-1.d: Exclude tic4x and tic54x.
+       * testsuite/gas/all/fill-1.s: Use L1 rather than .L1.
+
+2017-10-24  Andrew Waterman  <andrew@sifive.com>
+
+       * testsuite/gas/riscv/c-addi16sp-fail.d: New test.
+       * testsuite/gas/riscv/c-addi16sp-fail.l: Likewise.
+       * testsuite/gas/riscv/c-addi16sp-fail.s: Likewise.
+       * testsuite/gas/riscv/c-addi4spn-fail.d: Likewise.
+       * testsuite/gas/riscv/c-addi4spn-fail.l: Likewise.
+       * testsuite/gas/riscv/c-addi4spn-fail.s: Likewise.
+       * testsuite/gas/riscv/riscv.exp: Add new tests.
+
+2017-10-24  Andrew Waterman  <andrew@sifive.com>
+
+       * testsuite/gas/riscv/c-lui-fail.d: New testcase.
+       * gas/testsuite/gas/riscv/c-lui-fail.l: Likewise.
+       * gas/testsuite/gas/riscv/c-lui-fail.s: Likewise.
+       * gas/testsuite/gas/riscv/riscv.exp: Likewise.
+
+2017-10-24  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * config/tc-i386.c (md_pseudo_table): Add .code64 directive
+       only if BFD64 is defined.
+       * testsuite/gas/i386/code64-inval.l: New file.
+       * gas/testsuite/gas/i386/code64-inval.s: Likewise.
+       * gas/testsuite/gas/i386/code64.d: Likewise.
+       * gas/testsuite/gas/i386/code64.s: Likewise.
+       * testsuite/gas/i386/i386.exp: Run mixed-mode-reloc32,
+       att-regs, intel-regs, intel-expr and string-ok tests only if
+       assembler supports x86-64.  Run code64 and code64-inval.
+
+2017-10-23  Palmer Dabbelt  <palmer@dabbelt.com>
+
+       * config/tc-riscv.c (riscv_frag_align_code): Align code by 4
+       bytes on non-RVC systems.
+
 2017-10-23  Maciej W. Rozycki  <macro@imgtec.com>
 
        * config/tc-mips.c (mips_elf_final_processing): Don't set
This page took 0.027179 seconds and 4 git commands to generate.