AArch64: Add missing changelog for Update encodings for stg, st2g, stzg and st2zg
[deliverable/binutils-gdb.git] / gas / ChangeLog
index abc092310718234fa0ae74ef8009f4f3db394b9b..75b60e26313c634584e37dcd8ce717710ae401c7 100644 (file)
@@ -1,3 +1,134 @@
+2019-01-25  Sudakshina Das  <sudi.das@arm.com>
+
+       * config/tc-aarch64.c (warn_unpredictable_ldst): Exempt
+       stg, st2g, stzg and stz2g from Xt == Xn with writeback warning.
+       * testsuite/gas/aarch64/armv8_5-a-memtag.d: Change tests for
+       stg, stzg, st2g and stz2g.
+       * testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.
+       * testsuite/gas/aarch64/illegal-memtag.l: Likewise.
+       * testsuite/gas/aarch64/illegal-memtag.s: Likewise.
+
+2019-01-25  Sudakshina Das  <sudi.das@arm.com>
+
+       * testsuite/gas/aarch64/armv8_5-a-memtag.d: New tests for stzgm.
+       * testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.
+       * testsuite/gas/aarch64/illegal-memtag.l: Likewise.
+       * testsuite/gas/aarch64/illegal-memtag.s: Likewise.
+
+2019-01-25  Sudakshina Das  <sudi.das@arm.com>
+           Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
+
+       * config/tc-aarch64.c (parse_address_main): Remove support for
+       [base]! address expression.
+       (parse_operands): Remove support for AARCH64_OPND_ADDR_SIMPLE_2.
+       (warn_unpredictable_ldst): Remove support for ldstgv_indexed.
+       * testsuite/gas/aarch64/armv8_5-a-memtag.d: Remove tests for ldgv
+       and stgv.
+       * testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.
+       * testsuite/gas/aarch64/illegal-memtag.l: Likewise.
+       * testsuite/gas/aarch64/illegal-memtag.s: Likewise.
+
+2019-01-25  Wu Heng  <wu.heng@zte.com.cn>
+
+       PR gas/23940
+       * macro.c (getstring): Check array bound before accessing.
+
+2019-01-25  Alan Modra  <amodra@gmail.com>
+
+       PR 20902
+       PR 24125
+       * read.c (stringer): Delete assertion.
+
+2019-01-21  Nick Clifton  <nickc@redhat.com>
+
+       * po/uk.po: Updated Ukranian translation.
+
+2019-01-19  Nick Clifton  <nickc@redhat.com>
+
+       * config.in: Regenerate.
+       * configure: Regenerate.
+       * po/gas.pot: Regenerate.
+
+2018-06-24  Nick Clifton  <nickc@redhat.com>
+
+       2.32 branch created.
+
+2019-01-17  Tamar Christina  <tamar.christina@arm.com>
+
+       * testsuite/gas/arm/archv6t2-1-pe.d: New test.
+       * testsuite/gas/arm/archv6t2-1.d: Skip pe.
+       * testsuite/gas/arm/csdb.d: Skip pe.
+       * testsuite/gas/arm/sb-thumb1-pe.d: New test.
+       * testsuite/gas/arm/sb-thumb1.d: Skip pe.
+       * testsuite/gas/arm/sb-thumb2-pe.d: New test.
+       * testsuite/gas/arm/sb-thumb2.d: Skip pe.
+       * testsuite/gas/arm/udf.d: Skip pe.
+
+2019-01-16  Kito Cheng  <kito@andestech.com>
+
+       * testsuite/gas/riscv/attribute-empty.d: New.
+
+2019-01-16  Kito Cheng  <kito@andestech.com>
+           Nelson Chu  <nelson@andestech.com>
+
+       * config/tc-riscv.c (DEFAULT_RISCV_ATTR): Define to 0 if not defined.
+       (riscv_set_options): Add `arch_attr` field.
+       (riscv_opts): Set default value for arch_attr.
+       (riscv_write_out_arch_attr): New.
+       (riscv_set_public_attributes): Likewise.
+       (riscv_md_end): Likewise.
+       (riscv_convert_symbolic_attribute): Likewise.
+       (s_riscv_attribute): Likewise.
+       (explicit_arch_attr): Likewise.
+       (riscv_pseudo_table): Add .attribute to the table.
+       (options): Add OPTION_ARCH_ATTR and OPTION_NO_ARCH_ATTR
+       enumeration constants.
+       (md_longopts): Add `march-attr' and `mno-arch-attr' options.
+       (md_parse_option): Handle the new options.
+       (md_show_usage): Document the `march-attr' option.
+       * config/tc-riscv.h (md_end): Define as riscv_md_end
+       (riscv_md_end): Declare.
+       (CONVERT_SYMBOLIC_ATTRIBUTE): Define as
+       riscv_convert_symbolic_attribute.
+       (riscv_convert_symbolic_attribute): Declare.
+       (start_assemble): Declare.
+       * testsuite/gas/elf/elf.exp: Adjust test case for section2.e.
+       * testsuite/gas/elf/section2.e-riscv: New.
+       * testsuite/gas/riscv/attribute-01.d: New test
+       * testsuite/gas/riscv/attribute-02.d: Likewise.
+       * testsuite/gas/riscv/attribute-03.d: Likewise.
+       * testsuite/gas/riscv/attribute-04.d: Likewise.
+       * testsuite/gas/riscv/attribute-04.s: Likewise.
+       * testsuite/gas/riscv/attribute-05.d: Likewise.
+       * testsuite/gas/riscv/attribute-05.s: Likewise.
+       * testsuite/gas/riscv/attribute-06.d: Likewise.
+       * testsuite/gas/riscv/attribute-06.s: Likewise.
+       * testsuite/gas/riscv/attribute-07.d: Likewise.
+       * testsuite/gas/riscv/attribute-07.s: Likewise.
+       * testsuite/gas/riscv/attribute-08.d: Likewise.
+       * testsuite/gas/riscv/attribute-08.s: Likewise.
+       * testsuite/gas/riscv/attribute-unknown.d: Likewise.
+       * testsuite/gas/riscv/attribute-unknown.s: Likewise.
+       * testsuite/gas/riscv/empty.l: Likewise.
+       * doc/c-riscv.texi (.attribute): Add documentation.
+       * configure.ac (--enable-default-riscv-attribute): New options.
+       * configure: Re-generate.
+       * config.in: Re-generate.
+
+2019-01-16  John Darrington <john@darrington.wattle.id.au>
+
+       * config/tc-s12z.c (lex_reg_name): Compare the length of the strings
+       before the contents.
+       * testsuite/gas/s12z/labels.d: New file.
+       * testsuite/gas/s12z/labels.s: New file.
+       * testsuite/gas/s12z/s12z.exp: Add them.
+       * config/tc-s12z.c (tfr): Change as_bad to as_warn.
+       Also fix message typo and semantics.
+       * config/tc-s12z.c (emit_opr): Emit BFD_RELOC_S12Z_OPR instead of
+       BFD_RELOC_24.
+       * testsuite/gas/s12z/opr-indirect-expr.d: Expect R_S12Z_OPR instead
+       of R_S12Z_EXT24.
+
 2019-01-14  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 
        * config/tc-arm.c (arm_ext_v6k_v6t2): Define.
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