+2019-05-02 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/24485
+ * config/tc-i386.c (process_suffix): Issue a warning to IRET
+ without a suffix for .code16gcc.
+ * testsuite/gas/i386/jump16.s: Add tests for iretX.
+ * testsuite/gas/i386/jump16.d: Updated.
+ * testsuite/gas/i386/jump16.e: New file.
+
+2019-05-01 Sudakshina Das <sudi.das@arm.com>
+
+ * config/tc-aarch64.c (parse_operands): Add case for
+ AARCH64_OPND_TME_UIMM16.
+ (aarch64_features): Add "tme".
+ * doc/c-aarch64.texi: Document the same.
+ * testsuite/gas/aarch64/tme-invalid.d: New test.
+ * testsuite/gas/aarch64/tme-invalid.l: New test.
+ * testsuite/gas/aarch64/tme-invalid.s: New test.
+ * testsuite/gas/aarch64/tme.d: New test.
+ * testsuite/gas/aarch64/tme.s: New test.
+
+2019-04-29 John Darrington <john@darrington.wattle.id.au>
+
+ * testsuite/gas/s12z/truncated.d: New file.
+ * testsuite/gas/s12z/truncated.s: New file.
+ * testsuite/gas/s12z/s12z.exp: Add new test.
+
+2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
+ Faraz Shahbazker <fshahbazker@wavecomp.com>
+
+ * config/tc-mips.c (macro) <M_LLWP_AB, M_LLDP_AB, M_SCWP_AB,
+ M_SCDP_AB>: New cases and expansions for paired instructions.
+ * testsuite/gas/mips/llpscp-32.s: New test source.
+ * testsuite/gas/mips/llpscp-64.s: Likewise.
+ * testsuite/gas/mips/llpscp-32.d: New test.
+ * testsuite/gas/mips/llpscp-64.d: Likewise.
+ * testsuite/gas/mips/mips.exp: Run the new tests.
+ * testsuite/gas/mips/r6.s: Add new instructions to test source.
+ * testsuite/gas/mips/r6-64.s: Likewise.
+ * testsuite/gas/mips/r6-64-n32.d: Check new instructions.
+ * testsuite/gas/mips/r6-64-n64.d: Likewise.
+ * testsuite/gas/mips/r6-n32.d: Likewise.
+ * testsuite/gas/mips/r6-n64.d: Likwwise.
+ * testsuite/gas/mips/r6.d: Likewise.
+
+2019-04-26 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/24485
+ * config/tc-i386.c (process_suffix): Don't add DATA_PREFIX_OPCODE
+ to IRET for .code16gcc.
+ * testsuite/gas/i386/jump16.s: Add IRET tests.
+ * testsuite/gas/i386/jump16.d: Updated.
+
+2019-04-25 Alexandre Oliva <aoliva@redhat.com>
+ Alan Modra <amodra@gmail.com>
+
+ PR gas/24444
+ * frags.c (frag_gtoffset_p): New.
+ * frags.h (frag_gtoffset_p): Declare it.
+ * expr.c (resolve_expression): Use it.
+
+2019-04-24 Alan Modra <amodra@gmail.com>
+
+ PR 24444
+ * symbols.c (resolve_symbol_value): When handling symbols
+ marked as sy_flags.resolved, return correct value for the
+ case of expression symbols left as an O_symbol expression.
+ Merge O_symbol code handling undefined and common symbols with
+ code handling special cases of expression symbols. Use
+ seg_left to test for undefined and common symbols. Don't
+ leave an O_symbol expression when X_add_symbol resolves to
+ the absolute_section. Init final_val later.
+ * testsuite/gas/mmix/basep-7.d: Adjust expected output.
+
+2019-04-24 John Darrington <john@darrington.wattle.id.au>
+
+ * testsuite/gas/s12z/bit-manip-invalid.s: Extend test for BSET
+ and BCLR instructions with an invalid mode.
+ * testsuite/gas/s12z/bit-manip-invalid.d: ditto.
+
+2019-04-19 Nick Clifton <nickc@redhat.com>
+
+ PR 24464
+ * config/tc-rx.h (md_relax_frag): Pass the max_iterations variable
+ to the relaxation function.
+ * config/tc-rx.c (rx_relax_frag): Add new parameter - the maximum
+ number of iterations. Make sure that our internal iteration limit
+ does not exceed this external iteration limit.
+
+2019-04-18 Matthew Fortune <matthew.fortune@mips.com>
+
+ * config/tc-mips.c (match_non_zero_reg_operand): Update
+ warning message.
+ * testsuite/gas/mips/r6-branch-constraints.l: Likewise.
+
+2019-04-18 Jozef Lawrynowicz <jozef.l@mittosystems.com>
+
+ * config/tc-msp430.c (msp430_make_init_symbols): Define
+ __crt0_run_{preinit,init,fini}_array symbols if
+ .{preinit,init,fini}_array sections exist.
+ * testsuite/gas/msp430/fini-array.d: New test.
+ * testsuite/gas/msp430/init-array.d: New test.
+ * testsuite/gas/msp430/preinit-array.d: New test.
+ * testsuite/gas/msp430/fini-array.s: New test source.
+ * testsuite/gas/msp430/init-array.s: New test source.
+ * testsuite/gas/msp430/preinit-array.s: New test source.
+ * testsuite/gas/msp430/msp430.exp: Add new tests to driver.
+
+2019-04-17 Jozef Lawrynowicz <jozef.l@mittosystems.com>
+
+ * config/tc-msp430.c (msp430_make_init_symbols): Define __crt0_init_bss
+ symbol when .lower.bss or .either.bss sections exist.
+ Define __crt0_movedata when .lower.data or .either.data sections exist.
+ * testsuite/gas/msp430/either-data-bss-sym.d: New test.
+ * testsuite/gas/msp430/low-data-bss-sym.d: New test.
+ * testsuite/gas/msp430/either-data-bss-sym.s: New test source.
+ * testsuite/gas/msp430/low-data-bss-sym.s: New test source.
+ * testsuite/gas/msp430/msp430.exp: Run new tests.
+ Enable large code model when running -mdata-region={upper,either}
+ tests.
+
+2019-04-17 Jozef Lawrynowicz <jozef.l@mittosystems.com>
+
+ * config/tc-msp430.c (options): New OPTION_UNKNOWN_INTR_NOPS,
+ OPTION_NO_UNKNOWN_INTR_NOPS and do_unknown_interrupt_nops.
+ (md_parse_option): Handle OPTION_UNKNOWN_INTR_NOPS and
+ OPTION_NO_UNKNOWN_INTR_NOPS by setting do_unknown_interrupt_nops
+ accordingly.
+ (md_show_usage): Likewise.
+ (md_shortopts): Add "mu" for OPTION_UNKNOWN_INTR_NOPS and
+ "mU" for OPTION_NO_UNKNOWN_INTR_NOPS.
+ (md_longopts): Likewise.
+ (warn_eint_nop): Update comment.
+ (warn_unsure_interrupt): Don't warn if prev_insn_is_nop or
+ prev_insn_is_dint or we are assembling for 430 ISA.
+ (msp430_operands): Only call warn_unsure_interrupt if
+ do_unknown_interrupt_nops == TRUE.
+ * testsuite/gas/msp430/nop-unknown-intr.s: New test source file.
+ * testsuite/gas/msp430/nop-unknown-intr-430.d: New test.
+ * testsuite/gas/msp430/nop-unknown-intr-430x.d: New test.
+ * testsuite/gas/msp430/nop-unknown-intr-430x-ignore.d: New test.
+ * testsuite/gas/msp430/nop-unknown-intr-430.l: Warning output for new
+ test.
+ * testsuite/gas/msp430/nop-unknown-intr-430x.l: Likewise.
+ * testsuite/gas/msp430/msp430.exp: Add new tests to driver.
+
+2019-04-16 Alan Modra <amodra@gmail.com>
+
+ * testsuite/gas/all/weakref1.d: xfail nds32.
+
+2019-04-16 Alan Modra <amodra@gmail.com>
+
+ * testsuite/gas/all/gas.exp: Remove ns32k xfails.
+ * testsuite/gas/all/weakref1u.d: Don't run for ns32k-*-*.
+
+2019-04-16 Alan Modra <amodra@gmail.com>
+
+ * write.h: Don't include bit_fix.h.
+ (struct fix): Rearrange some fields. Delete fx_im_disp and
+ fx_bit_fixP. Use bitfields for fx_size and fx_pcrel_adjust.
+ * write.c (fix_new_internal): Don't init fx_im_disp and fx_bit_fixP.
+ (fixup_segment): Don't exclude overflow checks on fx_bit_fixP.
+ (print_fixup): Don't print im_disp.
+ * config/tc-cris.c (md_apply_fix): Remove tests of fx_bit_fixP
+ and fx_im_disp.
+ * config/tc-dlx.c (md_apply_fix): Remove wrong debug code. Set
+ fx_no_overflow when fx_bit_fixP.
+ * config/tc-dlx.h: Include bit_fix.h.
+ (TC_FIX_TYPE, tc_fix_data, TC_INIT_FIX_DATA): Define.
+ * config/tc-ns32k.c (fix_new_ns32k, fix_new_ns32k_exp): Set
+ fx_no_overflow when bit_fixP.
+ * config/tc-ns32k.h (TC_FIX_TYPE): Add fx_bit_fixP and fx_im_disp.
+ (fix_im_disp, fix_bit_fixP): Adjust to suit.
+ (TC_INIT_FIX_DATA, TC_FIX_DATA_PRINT): Likewise.
+
+2019-04-16 Alan Modra <amodra@gmail.com>
+
+ * write.h (struct fix <fx_where>): Make unsigned.
+ (fix_new, fix_at_start, fix_new_exp): Adjust prototypes.
+ * write.c (fix_new, fix_new_exp, fix_at_start): Make "where" and
+ "size" parameters unsigned long.
+ (fix_new_internal): Likewise. Adjust error format string to suit.
+ * config/tc-mips.c (md_convert_frag): Remove cast of fx_where.
+ * config/tc-sparc.c (md_apply_fix): Likewise.
+ * config/tc-score.c (s3_convert_frag): Adjust for unsigned fx_where.
+ * config/tc-score7.c (s7_convert_frag): Likewise.
+
+2019-04-16 Alan Modra <amodra@gmail.com>
+
+ * frags.h (struct frag <fr_fix>): Use unsigned type.
+ * frags.c (frag_new): Assert that current size exceeds
+ old_frags_var_max_size.
+ * ehopt.c (get_cie_info): Adjust for unsigned fr_fix.
+ * listing.c (calc_hex): Likewise.
+ * write.c (cvt_frag_to_fill, write_relocs): Likewise.
+ * config/tc-arc.c (md_convert_frag): Likewise.
+ * config/tc-avr.c (avr_patch_gccisr_frag): Likewise.
+ * config/tc-mips.c (md_convert_frag): Likewise.
+ * config/tc-rl78.c (md_convert_frag): Likewise.
+ * config/tc-rx.c (md_convert_frag): Likewise.
+ * config/tc-sparc.c (md_apply_fix): Likewise.
+ * config/tc-xtensa.c (next_instrs_are_b_retw): Likewise.
+ (unrelaxed_frag_min_insn_count, unrelaxed_frag_has_b_j): Likewise.
+
+2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * config/tc-arm.c (parse_sys_vldr_vstr): New function.
+ (OP_VLDR): New enum operand_parse_code enumerator.
+ (parse_operands): Add logic for OP_VLDR.
+ (do_t_vldr_vstr_sysreg): New function.
+ (do_vldr_vstr): Likewise.
+ (insns): Guard VLDR and VSTR by arm_ext_v4t for Thumb mode.
+ (md_apply_fix): Add bound check for VLDR and VSTR co-processor offset.
+ Add masking logic for BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM relocation.
+ * testsuite/gas/arm/archv8m_1m-cmse-main-bad.s: Add examples of bad
+ uses of VLDR and VSTR.
+ * testsuite/gas/arm/archv8m_1m-cmse-main-bad.l: Add error messages for
+ above bad uses.
+ * testsuite/gas/arm/archv8m_1m-cmse-main.s: Add examples of VLDR and
+ VSTR valid uses.
+ * testsuite/gas/arm/archv8m_1m-cmse-main.d: Add disassembly for the
+ above examples.
+
+2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * config/tc-arm.c (arm_typed_reg_parse): Fix typo in comment.
+ (enum reg_list_els): New REGLIST_VFP_S_VPR and REGLIST_VFP_D_VPR
+ enumerators.
+ (parse_vfp_reg_list): Add new partial_match parameter. Set
+ *partial_match to TRUE if at least one element in the register list has
+ matched. Add support for REGLIST_VFP_S_VPR and REGLIST_VFP_D_VPR
+ register lists which expect VPR as last element in the list.
+ (s_arm_unwind_save_vfp_armv6): Adapt call to parse_vfp_reg_list to new
+ prototype.
+ (s_arm_unwind_save_vfp): Likewise.
+ (enum operand_parse_code): New OP_VRSDVLST enumerator.
+ (parse_operands): Adapt call to parse_vfp_reg_list to new prototype.
+ Handle new OP_VRSDVLST case.
+ (do_t_vscclrm): New function.
+ (insns): New entry for VSCCLRM instruction.
+ * testsuite/gas/arm/archv8m_1m-cmse-main-bad.s: Add invalid VSCCLRM
+ instructions.
+ * testsuite/gas/arm/archv8m_1m-cmse-main-bad.l: Add error expectations
+ for above instructions.
+ * testsuite/gas/arm/archv8m_1m-cmse-main.s: Add tests for VSCCLRM
+ instruction.
+ * testsuite/gas/arm/archv8m_1m-cmse-main.d: Add expected disassembly
+ for above instructions.
+
+2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * config/tc-arm.c (enum reg_list_els): Define earlier and add
+ REGLIST_RN and REGLIST_CLRM enumerators.
+ (parse_reg_list): Add etype parameter to distinguish between regular
+ core register list and CLRM register list. Add logic to
+ recognize CLRM register list.
+ (parse_vfp_reg_list): Assert type is not for core register list.
+ (s_arm_unwind_save_core): Update call to parse_reg_list to new
+ prototype.
+ (enum operand_parse_code): Declare OP_CLRMLST enumerator.
+ (parse_operands): Update call to parse_reg_list to new prototype. Add
+ logic for OP_CLRMLST.
+ (encode_thumb2_ldmstm): Rename into ...
+ (encode_thumb2_multi): This. Add do_io parameter. Add logic to
+ encode CLRM and guard LDM/STM only code by do_io.
+ (do_t_ldmstm): Adapt to use encode_thumb2_multi.
+ (do_t_push_pop): Likewise.
+ (do_t_clrm): New function.
+ (insns): Define CLRM.
+ * testsuite/gas/arm/archv8m_1m-cmse-main-bad.d: New file.
+ * testsuite/gas/arm/archv8m_1m-cmse-main-bad.l: Likewise.
+ * testsuite/gas/arm/archv8m_1m-cmse-main-bad.s: Likewise.
+ * testsuite/gas/arm/archv8m_1m-cmse-main.d: Likewise.
+ * testsuite/gas/arm/archv8m_1m-cmse-main.s: Likewise.
+
+2019-04-15 Sudakshina Das <sudi.das@arm.com>
+ Andre Vieira <andre.simoesdiasvieira@arm.com>
+
+ * config/tc-arm.c (operand_parse_code): Add OP_LR and OP_oLR
+ for the LR operand and optional LR operand.
+ (parse_operands): Add switch cases for OP_LR and OP_oLR for
+ both type checking and value checking.
+ (encode_thumb32_addr_mode): New entries for DLS, WLS and LE.
+ (v8_1_loop_reloc): New helper function for handling labels
+ for the low overhead loop instructions.
+ (do_t_loloop): New function to encode DLS, WLS and LE.
+ (insns): New entries for WLS, DLS and LE.
+ (md_pcrel_from_section): New switch case
+ for BFD_RELOC_ARM_THUMB_LOOP12.
+ (md_appdy_fix): Likewise.
+ (tc_gen_reloc): Likewise.
+ * testsuite/gas/arm/armv8_1-m-tloop.s: New.
+ * testsuite/gas/arm/armv8_1-m-tloop.d: New.
+ * testsuite/gas/arm/armv8_1-m-tloop-bad.s: New.
+ * testsuite/gas/arm/armv8_1-m-tloop-bad.d: New.
+ * testsuite/gas/arm/armv8_1-m-tloop-bad.l: New.
+
+2019-04-15 Sudakshina Das <sudi.das@arm.com>
+ Andre Vieira <andre.simoesdiasvieira@arm.com>
+
+ * config/tc-arm.c (T16_32_TAB): New entriy for bfcsel.
+ (do_t_v8_1_branch): New switch case for bfcsel.
+ (toU): Define.
+ (insns): New instruction for bfcsel.
+ (md_pcrel_from_section): New switch case
+ for BFD_RELOC_THUMB_PCREL_BFCSEL.
+ (md_appdy_fix): Likewise
+ (tc_gen_reloc): Likewise.
+ * testsuite/gas/arm/armv8_1-m-bfcsel.d: New.
+ * testsuite/gas/arm/armv8_1-m-bfcsel.s: New.
+
+2019-04-15 Sudakshina Das <sudi.das@arm.com>
+
+ * config/tc-arm.c (md_pcrel_from_section): New switch case for
+ BFD_RELOC_ARM_THUMB_BF13.
+ (md_appdy_fix): Likewise.
+ (tc_gen_reloc): Likewise.
+
2019-04-15 Sudakshina Das <sudi.das@arm.com>
Andre Vieira <andre.simoesdiasvieira@arm.com>
projects / deliverable / binutils-gdb.git / blobdiff