+2016-11-01 Palmer Dabbelt <palmer@dabbelt.com>
+ Andrew Waterman <andrew@sifive.com>
+
+ Add support for RISC-V architecture.
+ * Makefile.am: Add riscv files.
+ * Makefile.in: Regenerate.
+ * NEWS: Mention the support for this architecture.
+ * configure.in: Define a default architecture.
+ * configure: Regenerate.
+ * configure.tgt: Add entries for riscv.
+ * doc/as.texinfo: Likewise.
+ * testsuite/gas/all/gas.exp: Expect the redef tests to fail.
+ * testsuite/gas/elf/elf.exp: Expect the groupauto tests to fail.
+ * config/tc-riscv.c: New file.
+ * config/tc-riscv.h: New file.
+ * doc/c-riscv.texi: New file.
+ * testsuite/gas/riscv: New directory.
+ * testsuite/gas/riscv/riscv.exp: New file.
+ * testsuite/gas/riscv/t_insns.d: New file.
+ * testsuite/gas/riscv/t_insns.s: New file.
+
+2016-10-27 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * config/tc-arc.c (arc_target): Delete.
+ (arc_target_name): Delete.
+ (arc_features): Delete.
+ (arc_mach_type): Delete.
+ (mach_type_specified_p): Delete.
+ (enum mach_selection_type): New enum.
+ (mach_selection_mode): New static global.
+ (selected_cpu): New static global.
+ (arc_eflag): Rename to ...
+ (arc_initial_eflag): ...this, and make const.
+ (arc_select_cpu): Update comment, new parameter, check how
+ previous machine type selection was made, and record this
+ selection. Use selected_cpu instead of old globals.
+ (arc_option): Remove use of arc_get_mach, instead use
+ arc_select_cpu to validate machine type selection. Use
+ selected_cpu over old globals.
+ (allocate_tok): Use selected_cpu over old globals.
+ (find_opcode_match): Likewise.
+ (assemble_tokens): Likewise.
+ (arc_cons_fix_new): Likewise.
+ (arc_extinsn): Likewise.
+ (arc_extcorereg): Likewise.
+ (md_begin): Update default machine type selection, use
+ selected_cpu over old globals.
+ (md_parse_option): Update machine type selection option handling,
+ use selected_cpu over old globals.
+ * testsuite/gas/arc/nps400-0.s: Add .cpu directive.
+
+2016-10-26 Alan Modra <amodra@gmail.com>
+
+ Revert 2016-10-06 Alan Modra <amodra@gmail.com>
+ * config/rl78-parse.y: Do use old %name-prefix syntax.
+ * config/rx-parse.y: Likewise.
+
+2016-10-21 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (cpu_arch): Remove .pcommit.
+ * doc/c-i386.texi: Likewise.
+ * testsuite/gas/i386/i386.exp: Remove pcommit tests.
+ * testsuite/gas/i386/pcommit-intel.d: Removed.
+ * testsuite/gas/i386/pcommit.d: Likewise.
+ * testsuite/gas/i386/pcommit.s: Likewise.
+ * testsuite/gas/i386/x86-64-pcommit-intel.d: Likewise.
+ * testsuite/gas/i386/x86-64-pcommit.d: Likewise.
+ * testsuite/gas/i386/x86-64-pcommit.s: Likewise.
+
+2016-10-20 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutis/20705
+ * testsuite/gas/i386/i386.exp: Run x86-64-opcode-bad.
+ * testsuite/gas/i386/x86-64-opcode-bad.d: New file.
+ * testsuite/gas/i386/x86-64-opcode-bad.s: Likewise.
+
+2016-10-19 Renlin Li <renlin.li@arm.com>
+
+ * config/tc-arm.c (encode_arm_shift): Generate unpredictable warning
+ for register-shifted register instructions.
+ * testsuite/gas/arm/shift-bad-pc.d: New.
+ * testsuite/gas/arm/shift-bad-pc.l: New.
+ * testsuite/gas/arm/shift-bad-pc.s: New.
+
+2016-10-17 Cupertino Miranda <cmiranda@synopsys.com>
+
+ * testsuite/arc/dis-inv.d: Fixed matching.
+
+2016-10-17 Cupertino Miranda <cmiranda@synopsys.com>
+
+ * testsuite/arc/dis-inv.s: Test to validate patch.
+ * testsuite/arc/dis-inv.d: Likewise.
+
+2016-10-14 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * testsuite/gas/arc/shortlimm_a7.d: New file.
+ * testsuite/gas/arc/shortlimm_a7.s: Likewise.
+ * testsuite/gas/arc/shortlimm_hs.d: Likewise.
+ * testsuite/gas/arc/shortlimm_hs.s: Likewise.
+
+2016-10-11 Nick Clifton <nickc@redhat.com>
+
+ * gas/arm/tls.d: Adjust output to match change in objdump.
+
+2016-10-11 Jiong Wang <jiong.wang@arm.com>
+
+ PR target/20666
+ * testsuite/gas/aarch64/alias-2.d: Update expected results.
+
+2016-10-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
+
+ * testsuite/gas/cfi/cfi-common-1.d: Adjust regexps for mips64.
+ * testsuite/gas/cfi/cfi-common-2.d: Likewise.
+ * testsuite/gas/cfi/cfi-common-3.d: Likewise.
+ * testsuite/gas/cfi/cfi-common-4.d: Likewise.
+ * testsuite/gas/cfi/cfi-common-5.d: Likewise.
+ * testsuite/gas/cfi/cfi-common-7.d: Likewise.
+ * testsuite/gas/cfi/cfi-common-8.d: Likewise.
+ * testsuite/gas/cfi/cfi-common-9.d: Likewise.
+ * testsuite/gas/cfi/cfi-mips-1.d: Likewise.
+
+2016-10-08 Alan Modra <amodra@gmail.com>
+
+ * Makefile.am (EXTRA_as_new_SOURCES): Add config/rl78-parse.y and
+ config/rx-parse.y. Move config/bfin-parse.y.
+ (bfin-parse.@OBJEXT@, rl78-parse.@OBJEXT@, rx-parse.@OBJEXT@): Delete.
+ ($(srcdir)/config/rl78-defs.h): New rule.
+ * Makefile.in: Regenerate.
+
+2016-10-07 Jiong Wang <jiong.wang@arm.com>
+
+ PR target/20667
+ * testsuite/gas/aarch64/sys-rt-reg.s: Test source for instructions using
+ SYS_Rt reg.
+ * testsuite/gas/aarch64/sys-rt-reg.d: New testcase.
+
+2016-10-06 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * testsuite/gas/arc/leave_enter.d: New file.
+ * testsuite/gas/arc/leave_enter.s: Likewise.
+ * testsuite/gas/arc/regnames.d: Likewise.
+ * testsuite/gas/arc/regnames.s: Likewise.
+ * config/tc-arc.c (arc_parse_name): Don't match reg names against
+ confirmed symbol names.
+
+2016-10-06 Alan Modra <amodra@gmail.com>
+
+ * app.c (do_scrub_chars): Move fall through comment.
+ * expr.c (operand): Likewise.
+
+2016-10-06 Matthew Fortune <matthew.fortune@imgtec.com>
+
+ PR gas/20648
+ * dw2gencfi.c (dot_cfi_sections): Refine the check for
+ inconsistent .cfi_sections to only consider compact vs non
+ compact forms.
+ * testsuite/gas/cfi/cfi-common-9.d: New file.
+ * testsuite/gas/cfi/cfi-common-9.s: New file.
+ * testsuite/gas/cfi/cfi.exp: Run new test.
+
+2016-10-06 Alan Modra <amodra@gmail.com>
+
+ * app.c: Add missing fall through comments.
+ * dw2gencfi.c: Likewise.
+ * expr.c: Likewise.
+ * config/tc-alpha.c: Likewise.
+ * config/tc-arc.c: Likewise.
+ * config/tc-arm.c: Likewise.
+ * config/tc-cr16.c: Likewise.
+ * config/tc-crx.c: Likewise.
+ * config/tc-dlx.c: Likewise.
+ * config/tc-h8300.c: Likewise.
+ * config/tc-hppa.c: Likewise.
+ * config/tc-i370.c: Likewise.
+ * config/tc-i386.c: Likewise.
+ * config/tc-i960.c: Likewise.
+ * config/tc-ia64.c: Likewise.
+ * config/tc-m68hc11.c: Likewise.
+ * config/tc-m68k.c: Likewise.
+ * config/tc-mep.c: Likewise.
+ * config/tc-metag.c: Likewise.
+ * config/tc-microblaze.c: Likewise.
+ * config/tc-mips.c: Likewise.
+ * config/tc-ns32k.c: Likewise.
+ * config/tc-rx.c: Likewise.
+ * config/tc-score.c: Likewise.
+ * config/tc-score7.c: Likewise.
+ * config/tc-sh.c: Likewise.
+ * config/tc-tic4x.c: Likewise.
+ * config/tc-vax.c: Likewise.
+ * config/tc-xstormy16.c: Likewise.
+ * config/tc-z80.c: Likewise.
+ * config/tc-z8k.c: Likewise.
+ * config/obj-elf.c: Likewise.
+ * config/tc-i386.c: Likewise.
+ * depend.c: Spell fall through comments consistently.
+ * config/tc-arm.c: Likewise.
+ * config/tc-d10v.c: Likewise.
+ * config/tc-i960.c: Likewise.
+ * config/tc-ia64.c: Likewise.
+ * config/tc-m68k.c: Likewise.
+ * config/tc-mcore.c: Likewise.
+ * config/tc-mep.c: Likewise.
+ * config/tc-ns32k.c: Likewise.
+ * config/tc-visium.c: Likewise.
+ * config/tc-xstormy16.c: Likewise.
+ * config/tc-z8k.c: Likewise.
+
+2016-10-06 Alan Modra <amodra@gmail.com>
+
+ * as.h (as_assert): Add ATTRIBUTE_NORETURN.
+
+2016-10-06 Alan Modra <amodra@gmail.com>
+
+ * config/tc-arc.c (find_opcode_match): Add missing break.
+ * config/tc-i960.c (get_cdisp): Likewise.
+ * config/tc-metag.c (parse_swap, md_apply_fix): Likewise.
+ * config/tc-mt.c (md_parse_option): Likewise.
+ * config/tc-nds32.c (nds32_apply_fix): Likewise.
+ * config/tc-hppa.c (pa_ip): Assert rather than testing last
+ condition of multiple if statements.
+ * config/tc-s390.c (s390_exp_compare): Return 0 on error.
+ * config/tc-tic4x.c (tic4x_operand_parse): Add as_bad and break
+ out of case rather than falling into next case. Formatting.
+
+2016-10-06 Alan Modra <amodra@gmail.com>
+
+ * config/rl78-parse.y: Don't use deprecated %name-prefix.
+ * config/rx-parse.y: Likewise.
+
+2016-09-29 Jiong Wang <jiong.wang@arm.com>
+
+ PR target/20553
+ * testsuite/gas/aarch64/advsimd-fp16.s (indexed_elem): New high index
+ testcases for H and S variants. New low index testcases for D variant.
+ * testsuite/gas/aarch64/advsimd-fp16.d: Update expected results.
+
+2016-09-29 Alan Modra <amodra@gmail.com>
+
+ * config/tc-ppc.c (md_assemble): Handle PPC_OPERAND_OPTIONAL32.
+ * testsuite/gas/ppc/power8.s: Provide tbegin. operand.
+ * testsuite/gas/ppc/power9.d: Update cmprb disassembly.
+
+2016-09-26 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
+
+ * config/tc-xtensa.c (xg_reverse_shift_count): Pass cnt_arg instead of
+ cnt_argp to concat.
+
+2016-09-26 Vlad Zakharov <vzakhar@synopsys.com>
+
+ * Makefile.in: Regenerate.
+ * configure: Likewise.
+ * doc/Makefile.in: Likewise.
+
+2016-09-26 Alan Modra <amodra@gmail.com>
+
+ * config/tc-ppc.c (ppc_elf_gnu_attribute): New function.
+ (md_pseudo_table <ELF>): Handle "gnu_attribute".
+
+2016-09-22 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * config/tc-arm.c (v7m_psrs): Remove BASEPRI_MASK MRS/MSR special
+ register and redundant basepri_max.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/tc-aarch64.c (print_operands): Print spaces between
+ operands.
+ * testsuite/gas/aarch64/ilp32-basic.d: Expect spaces after ","
+ in addresses.
+ * testsuite/gas/aarch64/ldst-reg-imm-post-ind.d: Likewise.
+ * testsuite/gas/aarch64/ldst-reg-imm-pre-ind.d: Likewise.
+ * testsuite/gas/aarch64/ldst-reg-pair.d: Likewise.
+ * testsuite/gas/aarch64/ldst-reg-reg-offset.d: Likewise.
+ * testsuite/gas/aarch64/ldst-reg-uns-imm.d: Likewise.
+ * testsuite/gas/aarch64/ldst-reg-unscaled-imm.d: Likewise.
+ * testsuite/gas/aarch64/reloc-insn.d: Likewise.
+ * testsuite/gas/aarch64/sve.d: Likewise.
+ * testsuite/gas/aarch64/symbol.d: Likewise.
+ * testsuite/gas/aarch64/system.d: Likewise.
+ * testsuite/gas/aarch64/tls-desc.d: Likewise.
+ * testsuite/gas/aarch64/sve-invalid.l: Expect spaces after ","
+ in suggested alternatives.
+ * testsuite/gas/aarch64/verbose-error.l: Likewise.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/tc-aarch64.c (output_operand_error_record): Use "must be"
+ rather than "should be" or "expected to be" in error messages.
+ (parse_operands): Likewise.
+ * testsuite/gas/aarch64/diagnostic.l: Likewise.
+ * testsuite/gas/aarch64/legacy_reg_names.l: Likewise.
+ * testsuite/gas/aarch64/sve-invalid.l: Likewise.
+ * testsuite/gas/aarch64/sve-reg-diagnostic.l: Likewise.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/tc-aarch64.c (opcode_lookup): Search for the end of
+ a condition name, rather than assuming that it will have exactly
+ 2 characters.
+ (parse_operands): Likewise.
+ * testsuite/gas/aarch64/alias.d: Add new condition-code comments
+ to the expected output.
+ * testsuite/gas/aarch64/beq_1.d: Likewise.
+ * testsuite/gas/aarch64/float-fp16.d: Likewise.
+ * testsuite/gas/aarch64/int-insns.d: Likewise.
+ * testsuite/gas/aarch64/no-aliases.d: Likewise.
+ * testsuite/gas/aarch64/programmer-friendly.d: Likewise.
+ * testsuite/gas/aarch64/reloc-insn.d: Likewise.
+ * testsuite/gas/aarch64/b_c_1.d, testsuite/gas/aarch64/b_c_1.s:
+ New test.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * testsuite/gas/aarch64/diagnostic.s,
+ testsuite/gas/aarch64/diagnostic.l: Add tests for
+ invalid uses of MUL VL and MUL in base AArch64 instructions.
+ * testsuite/gas/aarch64/sve-add.s, testsuite/gas/aarch64/sve-add.d,
+ testsuite/gas/aarch64/sve-dup.s, testsuite/gas/aarch64/sve-dup.d,
+ testsuite/gas/aarch64/sve-invalid.s,
+ testsuite/gas/aarch64/sve-invalid.d,
+ testsuite/gas/aarch64/sve-invalid.l,
+ testsuite/gas/aarch64/sve-reg-diagnostic.s,
+ testsuite/gas/aarch64/sve-reg-diagnostic.d,
+ testsuite/gas/aarch64/sve-reg-diagnostic.l,
+ testsuite/gas/aarch64/sve.s, testsuite/gas/aarch64/sve.d: New tests.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * doc/c-aarch64.texi: Document the "sve" feature.
+ * config/tc-aarch64.c (REG_TYPE_R_Z_BHSDQ_VZP): New register type.
+ (get_reg_expected_msg): Handle it.
+ (parse_operands): When parsing operands of an SVE instruction,
+ disallow immediates that match REG_TYPE_R_Z_BHSDQ_VZP.
+ (aarch64_features): Add an entry for SVE.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/tc-aarch64.c (parse_operands): Handle the new SVE core
+ and FP register operands.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/tc-aarch64.c (double_precision_operand_p): New function.
+ (parse_operands): Use it to calculate the dp_p input to
+ parse_aarch64_imm_float. Handle the new SVE FP immediate operands.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/tc-aarch64.c (parse_operands): Handle the new SVE integer
+ immediate operands.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/tc-aarch64.c (SHIFTED_NONE, SHIFTED_MUL_VL): New
+ parse_shift_modes.
+ (parse_shift): Handle SHIFTED_MUL_VL.
+ (parse_address_main): Add an imm_shift_mode parameter.
+ (parse_address, parse_sve_address): Update accordingly.
+ (parse_operands): Handle MUL VL addressing modes.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/tc-aarch64.c (REG_TYPE_SVE_BASE, REG_TYPE_SVE_OFFSET): New
+ register types.
+ (get_reg_expected_msg): Handle them.
+ (aarch64_addr_reg_parse): New function, split out from
+ aarch64_reg_parse_32_64. Handle Z registers too.
+ (aarch64_reg_parse_32_64): Call it.
+ (parse_address_main): Add base_qualifier, offset_qualifier,
+ base_type and offset_type parameters. Handle SVE base and offset
+ registers.
+ (parse_address): Update call to parse_address_main.
+ (parse_sve_address): New function.
+ (parse_operands): Parse the new SVE address operands.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/tc-aarch64.c (SHIFTED_MUL): New parse_shift_mode.
+ (parse_shift): Handle it. Reject AARCH64_MOD_MUL for all other
+ shift modes. Skip range tests for AARCH64_MOD_MUL.
+ (process_omitted_operand): Handle AARCH64_OPND_SVE_PATTERN_SCALED.
+ (parse_operands): Likewise.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/tc-aarch64.c (parse_enum_string): New function.
+ (po_enum_or_fail): New macro.
+ (parse_operands): Handle AARCH64_OPND_SVE_PATTERN and
+ AARCH64_OPND_SVE_PRFOP.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/tc-aarch64.c (vector_el_type): Add NT_zero and NT_merge.
+ (parse_vector_type_for_operand): Assert that the skipped character
+ is a '.'.
+ (parse_predication_for_operand): New function.
+ (parse_typed_reg): Parse /z and /m suffixes for predicate registers.
+ (vectype_to_qualifier): Handle NT_zero and NT_merge.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/tc-aarch64.c (NTA_HASVARWIDTH): New macro.
+ (AARCH64_REG_TYPES): Add ZN and PN.
+ (get_reg_expected_msg): Handle them.
+ (parse_vector_type_for_operand): Add a reg_type parameter.
+ Skip the width for Zn and Pn registers.
+ (parse_typed_reg): Extend vector handling to Zn and Pn. Update the
+ call to parse_vector_type_for_operand. Set HASVARTYPE for Zn and Pn,
+ expecting the width to be 0.
+ (parse_vector_reg_list): Restrict error about [BHSD]nn operands to
+ REG_TYPE_VN.
+ (vectype_to_qualifier): Use S_[BHSD] qualifiers for NTA_HASVARWIDTH.
+ (parse_operands): Handle the new Zn and Pn operands.
+ (REGSET16): New macro, split out from...
+ (REGSET31): ...here.
+ (reg_names): Add Zn and Pn entries.
+
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
* config/tc-aarch64.c (output_operand_error_record): Handle
projects / deliverable / binutils-gdb.git / blobdiff