+2005-09-08 Chao-ying Fu <fu@mips.com>
+
+ * doc/as.texinfo: Document -mdsp and -mno-dsp options.
+ * doc/c-mips.texi: Likewise, and document ".set dsp" and ".set nodsp"
+ directives.
+
+2005-09-08 Paul Brook <paul@codesourcery.com>
+
+ * config/tc-arm.c (do_smi, do_t_smi): Rename ...
+ (do_smc, do_t_smc): ... to this.
+ (insns): Remane smi to smc.
+ (md_apply_fix, tc_gen_reloc): Rename BFD_RELOC_ARM_SMI to
+ BFD_RELOC_ARM_SMC.
+
+2005-09-07 Richard Henderson <rth@redhat.com>
+
+ * dwarf2dbg.c (dwarf2_where): Set line->isa.
+ (dwarf2_set_isa): New.
+ (dwarf2_directive_loc): Rearrange to allow all options on one line.
+ * dwarf2dbg.h (dwarf2_set_isa): Declare.
+ * doc/as.texinfo: Update .loc documentation.
+
+2005-09-07 Richard Henderson <rth@redhat.com>
+
+ * dwarf2dbg.c: Include safe-ctype.h.
+ (DWARF2_LINE_OPCODE_BASE): Bump to 13.
+ (current): Initialize.
+ (dwarf2_emit_insn): Clear DWARF2_FLAG_BASIC_BLOCK,
+ DWARF2_FLAG_PROLOGUE_END, DWARF2_FLAG_EPILOGUE_BEGIN.
+ (dwarf2_directive_file): Cope with invalid filename.
+ (dwarf2_directive_loc): Add handling for basic_block, prologue_end,
+ epilogue_begin, is_stmt, isa.
+ (emit_inc_line_addr): Move line_delta == 0, addr_delta == 0 special
+ case down lower.
+ (process_entries): Handle isa, DWARF2_FLAG_PROLOGUE_END,
+ and DWARF2_FLAG_EPILOGUE_BEGIN.
+ (out_debug_line): Emit sizes for DW_LNS_set_prologue_end,
+ DW_LNS_set_epilogue_begin, DW_LNS_set_isa.
+ * dwarf2dbg.h (DWARF2_FLAG_IS_STMT): Rename from DWARF2_FLAG_BEGIN_STMT.
+ (DWARF2_FLAG_BASIC_BLOCK): Rename from DWARF2_FLAG_BEGIN_BLOCK.
+ (DWARF2_FLAG_PROLOGUE_END, DWARF2_FLAG_EPILOGUE_BEGIN): New.
+ (struct dwarf2_line_info): Add isa member.
+ * doc/as.texinfo (LNS directives): New node.
+
+2005-09-07 David Ung <davidu@mips.com>
+
+ * config/tc-mips.c (append_insn): Undo last change. Instead add
+ guard to suppress calling frag_grow if the current instruction is
+ one that allows a delay slot.
+
+2005-09-06 Chao-ying Fu <fu@mips.com>
+
+ * config/tc-mips.c (mips_set_options): Add ase_mt for MT instructions.
+ (mips_opts): Add -1 to initialize ase_mt.
+ (file_ase_mt): New variable for -mmt.
+ (CPU_HAS_MT): New define.
+ (validate_mips_insn): Add supports for +t, +T, !, $, *, &, g operand
+ formats.
+ (mips_ip): Check ase_mt to enable MT instructions.
+ Handle !, $, *, &, +T, +t, g operand formats.
+ For "mftc1", "mfthc1", "cftc1", "mttc1", "mtthc1", "cttc1", we allow
+ odd float registers.
+ (OPTION_MT, OPTION_NO_MT): New define.
+ (OPTION_COMPAT_ARCH_BASE): Change because of inserting MT define.
+ (md_parse_option): Parse OPTION_MT and OPTION_NO_MT.
+ (mips_after_parse_args): Set ase_mt based on CPU.
+ (s_mipsset): Handle ".set mt" and ".set nomt".
+ (mips_elf_final_processing): Remind of adding new flag for MT ASE.
+ (md_show_usage): Show usage of -mmt and -mno-mt.
+ * doc/as.texinfo: Document -mmt and -mno-mt options.
+ * doc/c-mips.texi: Likewise, and document ".set mt" and ".set nomt"
+ directives.
+
+2005-09-06 Paul Brook <paul@codesourcery.com>
+
+ * config/tc-arm.c (arm_it): Add relax field.
+ (T16_32_TAB): Add addi, addis, add_pc, add_sp, dec_sp, inc_sp,
+ b, bcond, ldr_pc, ldr_pc2, ldr_sp, str_sp, subi, subis.
+ (do_t_add_sub, do_t_addr, do_t_branch, do_t_ldst,
+ do_t_mov_cmp): Allow relaxation.
+ (output_relax_insn): New function.
+ (put_thumb32_insn): New function.
+ (output_inst): Use new functions.
+ (md_assemble): Don't throw error on relaxable instructions.
+ (insns): Change "b" entry from TCE(...) to tCE(...).
+ (md_estimate_size_before_relax): Return 2.
+ (md_convert_frag, relax_immediate, relax_adr, relax_addsub,
+ relax_branch, arm_relax_frag): New functions.
+ (arm_force_relocation): Return 0 for Thumb-2 immediate operand
+ relocations.
+ * config/tc-arm.h (md_convert_frag): Remove definition.
+ (md_relax_frag): Define.
+ (arm_relax_frag): Add prototype.
+
+2005-09-02 Paul Brook <paul@codesourcery.com>
+
+ * config/tc-arm.c (do_rn_rd): Enforce SWP operand constraints.
+
+2005-09-02 Paul Brook <paul@codesourcery.com>
+
+ * config/tc-arm.c (encode_arm_cp_address): Use
+ BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
+ (do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
+ mode.
+ (md_assemble): Only allow coprocessor instructions when Thumb-2 is
+ available.
+ (cCE, cC3): Define.
+ (insns): Use them for coprocessor instructions.
+ (md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
+ (get_thumb32_insn): New function.
+ (put_thumb32_insn): New function.
+ (md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
+ BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
+
+2005-09-02 Paul Brook <paul@codesourcery.com>
+
+ * config/tc-arm.c (opcode_lookup): Look for infix opcode when
+ incorrect suffix matches.
+
+2005-09-01 David Ung <davidu@mips.com>
+
+ * config/tc-mips.c (append_insn): Correctly handle mips16 case
+ when the frags are different for the 2 instructions we want to
+ swap. If the lengths of the 2 instructions are not the same, we
+ won't do the swap but emit an nop.
+
+2005-09-01 Dmitry Diky <diwil@spec.ru>
+
+ * config/tc-msp430.c (msp430_operands): Emit dwarf2_emit_insn()
+ as appropriate. Change frag_variant() to frag_var() for relaxes.
+
+2005-08-29 Nick Clifton <nickc@redhat.com>
+
+ * write.c (generic_force_reloc): Do not call S_FORCE_RELOC if
+ there is no symbol.
+
+2005-08-26 Jan Beulich <jbeulich@novell.com>
+
+ * config/tc-i386.c (intel_e09): Set JumpAbsolute when seeing a PTR-
+ qualified operand of a branch.
+ (intel_bracket_expr): Set JumpAbsolute here...
+ (intel_e11): ... rather than here.
+
+2005-08-26 Christian Groessler <chris@groessler.org>
+
+ * configure.tgt: Set bfd_gas also for z8k cpu.
+ * config/tc-z8k.c (s_segm): Use bfd_set_arch_mach to set machine
+ type.
+ (newfix): Adapt to bfd reloc types.
+ (build_bytes): Adapt to bfd reloc types. Ensure that enough space
+ is available in the current frag.
+ (md_convert_frag): Adapt function parameters.
+ (tc_gen_reloc): New function.
+ (md_section_align): Use bfd_get_section_alignment.
+ (md_apply_fix): Adapt to bfd reloc types. Fix handling of
+ BFD_RELOC_Z8K_IMM4L, BFD_RELOC_8, BFD_RELOC_16, and BFD_RELOC_32
+ relocations.
+ * config/tc-z8k.h (TARGET_ARCH): Define.
+ (tc_fix_adjustable): Define.
+
+2005-08-25 Chao-ying Fu <fu@mips.com>
+
+ * config/tc-mips.c (mips_set_options): Add ase_dsp for DSP instructions.
+ (mips_opts): Add -1 to initialize ase_dsp.
+ (file_ase_dsp): New variable for -mdsp.
+ (CPU_HAS_DSP): New define.
+ (validate_mips_insn): Add supports for 3, 4, 5, 6, 7, 8, 9, 0, ', :, @
+ operand formats.
+ (mips_ip): Add min_range and max_range for checking singed numbers.
+ Check ase_dsp to enable DSP instructions.
+ Handle 3, 4, 5, 6, 7, 8, 9, 0, ', :, @ operand formats.
+ (OPTION_DSP, OPTION_NO_DSP): New define.
+ (OPTION_COMPAT_ARCH_BASE): Change because of inserting DSP define.
+ (md_parse_option): Parse OPTION_DSP and OPTION_NO_DSP.
+ (mips_after_parse_args): Set ase_dsp based on CPU.
+ (s_mipsset): Handle ".set dsp" and ".set nodsp".
+ (mips_elf_final_processing): Remind of adding new flag for DSP ASE.
+ (md_show_usage): Show usage of -mdsp and -mno-dsp.
+
+2005-08-23 David Ung <davidu@mips.com>
+
+ * config/tc-mips.c (mips_cpu_info_table): Add 5kf to the table of
+ cpu names.
+
+2005-08-23 Alan Modra <amodra@bigpond.net.au>
+
+ PR 1036
+ * config/tc-ppc.c (ppc_symbol_chars): Add '%' and '['.
+
2005-08-23 Phil Edwards <phil@codesourcery.com>
* configure.tgt (*-*-vxworks): Match vxworks* instead.
projects / deliverable / binutils-gdb.git / blobdiff