+2018-03-28 Jan Beulich <jbeulich@suse.com>
+
+ * testsuite/gas/i386/ilp32/x86-64-simd-suffix.d,
+ testsuite/gas/i386/x86-64-simd-suffix.d: Drop q suffix from
+ cvt*2si.
+
+2018-03-28 Nick Clifton <nickc@redhat.com>
+
+ PR 22988
+ * config/tc-aarch64.c (parse_operands): Add code to handle
+ AARCH64_OPN_SVE_ADDR_R.
+ * testsuite/gas/aarch64/sve.s: Add tests for LDFF1xx instructions
+ with an assumed XZR offset address register.
+ * testsuite/gas/aarch64/sve.d: Update expected disassembly.
+
+2018-03-22 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (check_VecOperands): Latch
+ i.broadcast->operand into op.
+
+2018-03-22 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (match_template): Special case base opcode
+ 0xa0 with HLE prefix.
+ * testsuite/gas/i386/hle.s: Add mov-accumulator-to-disp cases.
+ * testsuite/gas/i386/hle.d, testsuite/gas/i386/hle-intel.d:
+ Adjust expectations.
+
+2018-03-22 Jan Beulich <jbeulich@suse.com>
+
+ * testsuite/gas/i386/opts.s: Add bndmov cases.
+ * testsuite/gas/i386/opts.d, testsuite/gas/i386/opts-intel.d,
+ testsuite/gas/i386/sse2avx-opts.d,
+ testsuite/gas/i386/sse2avx-opts-intel.d: Adjust expectations.
+
+2018-03-22 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (match_mem_size): Extend sub-xmmword
+ exceptions.
+ * testsuite/gas/i386/xmmword.l, testsuite/gas/i386/xmmword.s:
+ New.
+ * testsuite/gas/i386/i386.exp: Run new test.
+
+2018-03-22 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (match_template): Also match 2nd and 4th
+ operand's register sizes.
+ * testsuite/gas/i386/unspec.l, testsuite/gas/i386/unspec.s: New.
+ * testsuite/gas/i386/i386.exp: Run new test.
+
+2018-03-19 Nick Clifton <nickc@redhat.com>
+
+ * po/uk.po: Updated Ukranian translation.
+
+2018-03-16 Jim Wilson <jimw@sifive.com>
+
+ * config/tc-riscv.c (check_absolute_expr): Expand comment. New
+ parameter maybe_csr. If maybe_csr and O_symbol, print CSR name.
+ (riscv_ip): Add new argument to check_absolute_expr calls.
+ * testsuite/gas/riscv/bad-csr.d: New.
+ * testsuite/gas/riscv/bad-csr.l: New.
+ * testsuite/gas/riscv/bad-csr.s: New.
+
+2018-03-14 Kito Cheng <kito.cheng@gmail.com>
+
+ * config/tc-riscv.c (opcode_name_list): New.
+ (opcode_names_hash): Likewise.
+ (init_opcode_names_hash): Likewise.
+ (opcode_name_lookup): Likewise.
+ (validate_riscv_insn): New argument length, and add new format
+ which used in .insn directive.
+ (md_begin): Refine hash table initialization logic into
+ init_opcode_hash.
+ (init_opcode_hash): New.
+ (my_getOpcodeExpression): Parse opcode name for .insn.
+ (riscv_ip): New argument hash, able to handle .insn directive.
+ (s_riscv_insn): Handler for .insn directive.
+ (riscv_pseudo_table): New entry for .insn.
+ * doc/c-riscv.texi: Add documentation for .insn directive.
+ * testsuite/gas/riscv/insn.d: Add testcase for .insn directive.
+ * testsuite/gas/riscv/insn.s: Likewise.
+
+2018-03-13 Nick Clifton <nickc@redhat.com>
+
+ * po/ru.po: Updated Russian translation.
+
+2018-03-09 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (optimize_encoding): Encode EVEX instructions
+ with VEX128 if EVEX encoding isn't required.
+ * testsuite/gas/i386/optimize-1.d: Updated.
+ * testsuite/gas/i386/x86-64-optimize-2.d: Likewise.
+
+2018-03-09 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (check_VecOperations): Strip whitespace.
+ * testsuite/gas/i386/optimize-1.s: Add whitespaces before
+ {%k7} and {z},
+ * testsuite/gas/i386/x86-64-optimize-2.s: Likewise.
+
+2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (set_cpu_arch): Set cpu_arch_isa_flags.
+ (md_parse_option): Likewise.
+ (optimize_encoding): Check i.tm.cpu_flags and cpu_arch_isa_flags
+ for cpuavx512vl instead of cpu_arch_flags. Optimize EVEX with
+ EVEX128 when EVEX encoding is required.
+ * testsuite/gas/i386/i386.exp: Run optimize-4, optimize-5,
+ x86-64-optimize-5 and x86-64-optimize-6.
+ * testsuite/gas/i386/optimize-1.d: Updated.
+ * testsuite/gas/i386/x86-64-optimize-2.d: Likewise.
+ * testsuite/gas/i386/optimize-4.d: New file.
+ * testsuite/gas/i386/optimize-4.s: Likewise.
+ * testsuite/gas/i386/optimize-5.d: Likewise.
+ * testsuite/gas/i386/optimize-5.s: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-5.d: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-5.s: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-6.d: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-6.s: Likewise.
+
+2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (optimize_encoding): Also encode "clr reg64"
+ as "xor reg32, reg32".
+ * testsuite/gas/i386/x86-64-optimize-1.s: Add "clr reg64" tests.
+ * testsuite/gas/i386/x86-64-optimize-1.d: Updated.
+
+2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
+
+ * NEWS: Mention -mold-gcc removal.
+ * config/tc-i386.c (i386_error): Remove old_gcc_only.
+ (old_gcc): Removed.
+ (match_template): Remove old gcc support.
+ (OPTION_MOLD_GCC): Removed.
+ (OPTION_MRELAX_RELOCATIONS): Updated.
+ (md_longopts): Remove OPTION_MOLD_GCC.
+ (md_parse_option): Likewise.
+ (md_show_usage): Remove -mold-gcc.
+ * testsuite/gas/i386/general.s: Convert fsub/fdiv tests for old
+ (<= 2.8.1) versions of gcc.
+ * testsuite/gas/i386/intel.s: Likewise.
+ * testsuite/gas/i386/general.l: Updated.
+ * testsuite/gas/i386/intel-intel.d: Likewise.
+ * testsuite/gas/i386/intel.d: Likewise.
+ * testsuite/gas/i386/intel.e: Likewise.
+ * testsuite/gas/i386/i386.exp: Don't pass -mold-gcc to general.
+
+2018-03-08 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (is_evex_encoding): New.
+ (optimize_encoding, md_assemble, md_assemble,
+ VEX_check_operands, build_modrm_byte): Use is_evex_encoding.
+ (build_evex_prefix): Derive EVEX length field from actual
+ operands if the template allows multiple ones.
+
+2018-03-08 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (build_modrm_byte): Make VexNDD handling cope
+ with 3rd (immediate) operand.
+
+2018-03-08 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (XMMWORD_MNEM_SUFFIX, YMMWORD_MNEM_SUFFIX,
+ ZMMWORD_MNEM_SUFFIX): Delete.
+ (process_suffix): Drop their uses. Re-arrange final part of
+ logic into a switch() statement. Drop special casing of
+ cmpxchg8b.
+
+2018-03-08 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (match_template): Also match register
+ operands 0 and 2 for 3-operand forms.
+ * testsuite/gas/i386/unspec64.l, testsuite/gas/i386/unspec64.s:
+ New.
+ * testsuite/gas/i386/i386.exp: Run new test.
+
+2018-03-08 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (process_suffix): Do common part of register
+ checks first.
+
+2018-03-08 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (parse_insn): Move success return up. Combine
+ failure returns.
+
+2018-03-08 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (cpu_flags_match): Add GFNI check to AVX
+ logic. Add respective logic for AVX512F.
+ * testsuite/gas/i386/arch-avx-1.s: Add GFNI test.
+ testsuite/gas/i386/arch-avx-1.d,
+ testsuite/gas/i386/arch-avx-1-1.l,
+ testsuite/gas/i386/arch-avx-1-2.l,
+ testsuite/gas/i386/arch-avx-1-3.l,
+ testsuite/gas/i386/arch-avx-1-4.l,
+ testsuite/gas/i386/arch-avx-1-5.l,
+ testsuite/gas/i386/arch-avx-1-6.l: Adjust expectations.
+ * testsuite/gas/i386/arch-avx-1-7.l,
+ testsuite/gas/i386/arch-avx-1-7.s,
+ testsuite/gas/i386/arch-avx-1-8.l,
+ testsuite/gas/i386/arch-avx-1-8.s,
+ testsuite/gas/i386/avx512f-plain.l,
+ testsuite/gas/i386/avx512f-plain.s,
+ testsuite/gas/i386/avx512vl-plain.l,
+ testsuite/gas/i386/avx512vl-plain.s: New.
+ * testsuite/gas/i386/i386.exp: Run new tests.
+
+2018-03-08 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (cpu_flags_match): Move AVX512VL check ahead.
+
+2018-03-08 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (CPU_FLAGS_32BIT_MATCH): Delete.
+ (cpu_flags_match): Use CPU_FLAGS_ARCH_MATCH instead of
+ CPU_FLAGS_32BIT_MATCH.
+
2018-03-08 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (CPU_FLAGS_AES_MATCH, CPU_FLAGS_AVX_MATCH,
projects / deliverable / binutils-gdb.git / blobdiff