+2000-03-09 Catherine Moore <clm@cygnus.com>
+
+ * config/tc-m32r.c (m32r_fix_adjustable): Look up the
+ relocation type based on the entry in the fixup structure.
+
+2000-03-08 H.J. Lu (hjl@gnu.org)
+
+ * Makefile.am (install-exec-tooldir): Depend on
+ install-exec-bindir for parallel make.
+ * Makefile.in: Regenerated.
+
+2000-03-06 Nick Clifton <nickc@cygnus.com>
+
+ * config/tc-m32r.c (struct md_longopts): Add -m32r command line
+ switch.
+ (md_parse_option): Parse -m32r command line switch - disable m32rx
+ compatability.
+ (md_show_usage): Document new option.
+
+ * doc/Makefile.am (CPU_DOCS): Add c-m32r.texi.
+ * doc/Makefile.in: Regenerate.
+ * doc/c-m32r.texi (M32R-Opts): Document new command line switch.
+
+2000-03-02 Michael Meissner <meissner@redhat.com>
+
+ * config/tc-d30v.c (check_range): Remove code that incorrectly
+ sign extended values where bits < 32.
+
+2000-03-02 H.J. Lu (hjl@gnu.org)
+
+ * configure.in: Support --enable-targets=all on ia32.
+ * configure: Regenerated.
+
+2000-03-01 Nick Clifton <nickc@cygnus.com>
+
+ * gasp.c (do_align): Remove bogus check of alignment value.
+
+2000-02-27 Thomas de Lellis <tdel@windriver.com>
+
+ * config/obj-elf.c (elf_frob_symbol): Remove code which when
+ TC_PPC was defined forced the type of a symbol with no other type
+ to be BSF_OBJECT.
+
+2000-02-27 Hans-Peter Nilsson <hp@axis.com>
+
+ * doc/internals.texi (CPU backend): Mention that
+ line_separator_chars do not break up comments. Fix typos for
+ LEX_AT and LEX_NAME descriptions. Document operands for
+ TC_EQUAL_IN_INSN, md_operand and md_section_align. Correct
+ description of md_create_short_jump usage. Document argument for
+ md_undefined_symbol.
+
+2000-02-27 Jakub Jelinek <jakub@redhat.com>
+
+ * config/tc-sparc.c (OPTION_UNDECLARED_REGS): New option.
+ (md_parse_option): Handle it.
+ (md_show_usage): Document it.
+
+2000-02-27 Ian Lance Taylor <ian@zembu.com>
+
+ * config/tc-alpha.c (md_assemble): Accept `1' and `9' in an
+ opcode, for the instruction `pal19'. From Andrea Arcangeli
+ <andrea@suse.de>.
+
+2000-02-26 Alan Modra <alan@spri.levels.unisa.edu.au>
+
+ * config/tc-i386.c (i386_immediate): Move constant operand sizing
+ from here..
+ (md_assemble): To here, before template operands are matched.
+ Also ensure a constant immediate is sign extended when we know the
+ size is at most 16 bits. This is to catch cases like "add
+ $0xffc0,%ax" where we don't know the size, and thus that the
+ immediate can be represented as Imm8S until after parsing the
+ register operand.
+ (i386_displacement): Similarly sign extend 16 bit constant
+ displacements.
+ (md_assemble): Relax 16-bit jump constant range check to suit sign
+ extended displacements.
+
+2000-02-26 Andreas Jaeger <aj@suse.de>
+
+ * doc/c-mips.texi (MIPS Opts): Fix typo in last patch.
+
+2000-02-25 Alan Modra <alan@spri.levels.unisa.edu.au>
+
+ * config/tc-i386.c (md_assemble): Don't swap intersegment jmp and
+ call operands when intel_syntax.
+ (intel_float_operand): Return 2 for "fi...".
+ (i386_operand_modifier): Change "DWORD PTR" test to suit above.
+ Return SHORT_MNEM_SUFFIX for "WORD PTR" when "fi...". Revert
+ earlier "SHORT" change.
+ (md_assemble): When determining suffix from Regs, exclude
+ InOutPortReg.
+
+2000-02-24 Nick Clifton <nickc@cygnus.com>
+
+ * configure: Add arm-wince, mips-pe and sh-pe targets.
+ * configure: Regenerate.
+
+ * config/obj-coff.h (COFF_WITH_PE): Define for mips-pe and
+ sh-pe targets.
+ (TARGET_FORMAT): Set to "pe-shl" for the sh-pe target and to
+ "pe-mips" for the mips-pe target.
+
+ * config/tc-arm.c (insns): Change displacement encoded in BL
+ and B instructions if the target port is arm-wince.
+ (do_ldst): Do not bias the relocation offset if the target
+ port is arm-wince.
+ (md_pcrel_from): Add in missing relocation offset bias if the
+ target os arm-wince.
+
+ * config/tc-mips.c (mips_target_format): Support COFF flavour.
+ (md_begin): Disable -G support for mips-pe target.
+ (md_apply_fix): Treat BFD_RELOC_RVA reloc as BFD_RELOC_32.
+ * config/tc-mips.h (USE_GLOBAL_POINTER_OPT): Add support for
+ COFF flavour.
+
+ * config/tc-sh.c (md_begin): sh-pe target is little endian.
+ * config/tc-sh.h (SUB_SEGMENT_ALIGN): If using a BFD
+ assembler, just set the alignment to 4.
+
+ * config/te-wince-pe.h: New file for WinCE targets. Define
+ TE_WINCE.
+
+2000-02-25 Alan Modra <alan@spri.levels.unisa.edu.au>
+
+ * config/tc-i386.c (md_assemble): Swap segments too for intel mode
+ string instructions.
+ (i386_operand_modifier): Set i.suffix = WORD_MNEM_SUFFIX for SHORT.
+ (i386_intel_memory_operand): After finding a segment override,
+ check again for no `[' before looking for a displacement. Bomb if
+ more than one displacement rather than silently discarding the
+ second and subsequent ones. Free strings malloc'd by
+ build_displacement_string.
+
+2000-02-24 Catherine Moore <clm@cygnus.com>
+
+ * config/obj-som.c (obj_pseudo_table): Add "weak".
+ (obj_som_weak): New routine.
+
+2000-02-24 Alan Modra <alan@spri.levels.unisa.edu.au>
+
+ * config/tc-i386.c (union i386_op): New.
+ (struct _i386_insn): Delete disps[], imms[], regs[]. Add op[].
+ Throughout file replace occurences of disps[n], imms[n], regs[n]
+ with equivalent op[n].disps, op[n].imms, op[n].regs. Simplify
+ intel mode operand swapping. Add assert in regKludge and
+ fake_zero_displacement code. Test i.types[n] when outputting
+ displacements and immediates. Combine output of Disp16 with
+ Disp32.
+ (md_assemble): Don't try to fix broken UNIXWARE_COMPAT opcodes
+ when in intel mode by (not) reversing fsub and fdiv operands
+ before the template search. This fails for single operand
+ shorthand forms of the instruction, and if UNIXWARE_COMPAT is
+ undefined. Instead fix the base_opcode after we've found the
+ template. Move base_opcode xor with found_reverse_match from
+ opcode output code to before this fix so we test for the correct
+ opcodes.
+ (md_assemble): Don't use strcmp when deciding to ignore the suffix
+ check in intel mode. Instead compare opcodes.
+
+ * config/tc-i386.h (TC_RELOC): Delete.
+ * config/tc-i386.c (TC_RELOC): Delete. Replace usage of TC_RELOC
+ with equivalent call to reloc.
+
+ * as.h (flag_m68k_mri): Move declaration after target include, and
+ only declare when TC_M68K defined. Define as zero otherwise.
+ (LABELS_WITHOUT_COLONS, NO_PSEUDO_DOT): If undefined, define as 0.
+ * app.c (scrub_m68k_mri): Declare only when TC_M68K defined.
+ Define as zero otherwise.
+ (do_scrub_begin): Use m68k_mri parameter only when TC_M68K defined.
+ (struct app_save): Declare scrub_m68k_mri only when TC_M68K.
+ (app_push, app_pop): Save scrub_m68k_mri only when TC_M68K.
+ (do_scrub_chars): Use LABELS_WITHOUT_COLONS directly rather than
+ testing whether defined.
+ * cond.c (ignore_input): Use NO_PSEUDO_DOT directly.
+ * expr.c (operand): #ifdef unused case labels when TC_M68K undefined.
+ * read.c: Use LABELS_WITHOUT_COLONS and NO_PSEUDO_DOT directly
+ rather than testing whether defined.
+ (s_mri): Set flag_m68k_mri only when TC_M68K defined.
+ (parse_mri_cons): Declare and use only when TC_M68K.
+ * config/tc-hppa.h (LABELS_WITHOUT_COLONS): Define as 1.
+ * config/tc-m68k.h (NO_PSEUDO_DOT): Define as 1.
+ * config/tc-m88k.h (NO_PSEUDO_DOT): Define as 1.
+
+ * NEWS: Mention IBM 370 support.
+
+2000-02-23 Richard Henderson <rth@cygnus.com>
+
+ * config/tc-i386.c (md_assemble): When swapping operands for
+ intel_syntax, assume everything that's not Imm or Disp is a
+ register.
+
+2000-02-23 Linas Vepstas <linas@linas.org>
+
+ * config/tc-i370.c, config/tc-i370.h: New files.
+ * Makefile.am: Add support for Linux/IBM 370.
+ * configure.in: Likewise.
+ * app.c (do_scrub_begin): Don't lex single quote when TC_I370.
+ * config/obj-elf.c: Include elf/i370.h
+ (obj_elf_section): Don't do anything special for flag_mri if TC_I370.
+
+ * Makefile.in: Regenerate.
+ * configure: Regenerate.
+
+ * doc/c-i370.texi: New file.
+ * doc/all.texi: Include it.
+ * doc/as.texinfo: And here.
+ * doc/Makefile.am(CPU_DOCS): Add c-i370.texi.
+ * doc/Makefile.in: Regenerate.
+
+2000-02-19 Michael Meissner <meissner@redhat.com>
+
+ * config/tc-d30v.c (parallel_ok): Use FLAG_NOT_WITH_ADDSUBppp to
+ determine if an instruction can be used in parallel with an ADDppp
+ or SUBppp instruction.
+
+2000-02-22 Andrew Haley <aph@cygnus.com>
+
+ * doc/c-mips.texi (MIPS Opts): Document -mgp32 and -mgp64.
+
+1999-12-30 Andrew Haley <aph@cygnus.com>
+
+ * config/tc-mips.c (mips_gp32): New variable.
+ (macro_build) Use mips_gp32.
+ (mips_ip): Ditto.
+ (md_longopts): Add "-mgp32" and "-mgp64".
+ (md_parse_option): Add OPTION_GP32 and OPTION_GP64.
+
+2000-02-22 Alexandre Oliva <oliva@lsd.ic.unicamp.br>
+
+ * config/obj-coff.c (add_lineno): Accept non-positive lineno with
+ warning, and bump it to 1.
+
2000-02-22 Ian Lance Taylor <ian@zembu.com>
From Brad Lucier <lucier@math.purdue.edu>:
projects / deliverable / binutils-gdb.git / blobdiff