+2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * testsuite/gas/arc/leave_enter.d: Update test.
+ * testsuite/gas/arc/leave_enter.s: Likewise.
+
+2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * testsuite/gas/arc/b.d: Update test.
+ * testsuite/gas/arc/noargs_hs.d: Likewise.
+
+2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
+
+ * config/tc-mips.c (md_convert_frag): Correct
+ BFD_RELOC_MIPS16_16_PCREL_S1 fixup size.
+ * testsuite/gas/mips/mips16-branch-addend-4.d: New test.
+ * testsuite/gas/mips/mips16-branch-addend-5.d: New test.
+ * testsuite/gas/mips/mips16-branch-addend-5.l: New stderr
+ output.
+ * testsuite/gas/mips/mips16-branch-addend-4.s: New test source.
+ * testsuite/gas/mips/mips16-branch-addend-5.s: New test source.
+ * testsuite/gas/mips/mips.exp: Run the new tests.
+
+2017-04-25 Jose E. Marchesi <jose.marchesi@oracle.com>
+
+ PR gas/21407
+ * config/tc-sparc.c (md_apply_fix): Do not transform `call'
+ instructions into branch instructions in fixups generating
+ additional relocations.
+ * testsuite/gas/sparc/call-relax.s: New file.
+ * testsuite/gas/sparc/call-relax.d: Likewise.
+ * testsuite/gas/sparc/call-relax-aout.d: Likewise.
+ * testsuite/gas/sparc/sparc.exp: Test call-relax and call-relax-aout.
+
+2017-04-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * config/tc-arm.c (move_or_literal_pool): Remove code generating MOVS.
+ Forbid MOV.W and MOVW if destination is SP or PC.
+ * testsuite/gas/arm/thumb2_ldr_immediate_highregs_armv6t2.s: Explain
+ expectation of LDR not generating a MOVS for low registers and small
+ constants. Add tests of MOVW generation.
+ * testsuite/gas/arm/thumb2_ldr_immediate_highregs_armv6t2.d: Update
+ expected disassembly.
+
+2017-04-22 Alan Modra <amodra@gmail.com>
+
+ * testsuite/gas/ppc/vle.s: Format. Add se_rfgi and e_sc.
+ * testsuite/gas/ppc/vle.d: Update.
+
+2017-04-21 Nick Clifton <nickc@redhat.com>
+
+ PR binutils/21380
+ * testsuite/gas/aarch64/illegal-3.s: New file.
+ * testsuite/gas/aarch64/illegal-3.d: New file.
+
+2017-04-11 Alan Modra <amodra@gmail.com>
+
+ * config/tc-ppc.c (md_show_usage): Delete mention of -mhtm.
+ * testsuite/gas/ppc/htm.d: Pass -mpower8 and -Mpower8.
+
+2017-04-10 Max Filippov <jcmvbkbc@gmail.com>
+
+ * config/tc-xtensa.c (xtensa_maybe_create_literal_pool_frag):
+ Initialize lps->frag_count with auto_litpool_limit.
+ (xg_promote_candidate_litpool): New function.
+ (xtensa_move_literals): Extract candidate litpool promotion code
+ into separate function. Call it for all possible found
+ candidates.
+ (xtensa_switch_to_literal_fragment): Drop 'recursive' flag and
+ call to xtensa_mark_literal_pool_location that it guards.
+ Replace it with call to xtensa_maybe_create_literal_pool_frag.
+ Initialize pool_location with created literal pool candidate.
+ * testsuite/gas/xtensa/all.exp: Add new tests.
+ * testsuite/gas/xtensa/auto-litpools-first1.d: New test results.
+ * testsuite/gas/xtensa/auto-litpools-first1.s: New test.
+ * testsuite/gas/xtensa/auto-litpools-first2.d: New test results.
+ * testsuite/gas/xtensa/auto-litpools-first2.s: New test.
+ * testsuite/gas/xtensa/auto-litpools.d: Fix offsets changed due
+ to additional jump instruction.
+
+2017-04-07 Alan Modra <amodra@gmail.com>
+
+ * testsuite/gas/ppc/altivec2.s: Delete E6500 vector insns.
+ * testsuite/gas/ppc/altivec2.d: Adjust to suit.
+
+2017-04-07 Alan Modra <amodra@gmail.com>
+
+ * testsuite/gas/elf/section12a.d: Don't expect alignment of 1
+ for .mbind.text.
+
+2017-04-06 Pip Cet <pipcet@gmail.com>
+
+ * testsuite/gas/wasm32/allinsn.d: Adjust test for disassembler
+ changes.
+ * testsuite/gas/wasm32/disass.d: New test.
+ * testsuite/gas/wasm32/disass.s: New test.
+ * testsuite/gas/wasm32/disass-2.d: New test.
+ * testsuite/gas/wasm32/disass-2.s: New test.
+ * testsuite/gas/wasm32/reloc.d: Adjust test for changed reloc
+ names.
+ * testsuite/gas/wasm32/reloc.s: Update test for changed assembler
+ syntax.
+ * testsuite/gas/wasm32/wasm32.exp: Run new tests. Expect allinsn
+ test to succeed.
+
+2017-04-04 H.J. Lu <hongjiu.lu@intel.com>
+
+ * NEWS: Mention support for ELF SHF_GNU_MBIND.
+ * config/obj-elf.c (section_match): New.
+ (get_section): Match both sh_info and group name.
+ (obj_elf_change_section): Add argument for sh_info. Pass both
+ sh_info and group name to get_section. Issue an error for
+ SHF_GNU_MBIND section without SHF_ALLOC. Set sh_info.
+ (obj_elf_parse_section_letters): Set SHF_GNU_MBIND for 'd'.
+ (obj_elf_section): Support SHF_GNU_MBIND section info.
+ * config/obj-elf.h (obj_elf_change_section): Add argument for
+ sh_info.
+ * config/tc-arm.c (start_unwind_section): Pass 0 as sh_info to
+ obj_elf_change_section.
+ * config/tc-ia64.c (obj_elf_vms_common): Likewise.
+ * config/tc-microblaze.c (microblaze_s_data): Likewise.
+ (microblaze_s_sdata): Likewise.
+ (microblaze_s_rdata): Likewise.
+ (microblaze_s_bss): Likewise.
+ * config/tc-mips.c (s_change_section): Likewise.
+ * config/tc-msp430.c (msp430_profiler): Likewise.
+ * config/tc-rx.c (parse_rx_section): Likewise.
+ * config/tc-tic6x.c (tic6x_start_unwind_section): Likewise.
+ * doc/as.texinfo: Document 'd' for SHF_GNU_MBIND.
+ * testsuite/gas/elf/elf.exp: Run section12a, section12b and
+ section13.
+ * testsuite/gas/elf/section10.d: Updated.
+ * testsuite/gas/elf/section10.s: Likewise.
+ * testsuite/gas/elf/section12.s: New file.
+ * testsuite/gas/elf/section12a.d: Likewise.
+ * testsuite/gas/elf/section12b.d: Likewise.
+ * testsuite/gas/elf/section13.l: Likewise.
+ * testsuite/gas/elf/section13.d: Likewise.
+ * testsuite/gas/elf/section13.s: Likewise.
+
+2017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
+
+ * config/tc-riscv.c (riscv_clear_subsets): Cast argument to free to
+ avoid const warnings.
+
+2017-03-30 Palmer Dabbelt <palmer@dabbelt.com>
+
+ * config/tc-riscv.c (riscv_clear_subsets): New function.
+ (riscv_add_subset): Call riscv_clear_subsets and riscv_set_rvc to
+ clear RVC when it's been previously set.
+
+2017-03-31 Nick Clifton <nickc@redhat.com>
+
+ PR gas/21333
+ * config/tc-s390.c (tc_s390_fix_adjustable): Allow non pc-relative
+ fixups in mergeable sections to be adjusted.
+
+2017-03-30 Pip Cet <pipcet@gmail.com>
+
+ * config/tc-wasm32.h: New file: Add WebAssembly assembler target.
+ * config/tc-wasm32.c: New file: Add WebAssembly assembler target.
+ * Makefile.am: Add WebAssembly assembler target.
+ * configure.tgt: Add WebAssembly assembler target.
+ * doc/c-wasm32.texi: New file: Start documenting WebAssembly
+ assembler.
+ * doc/all.texi: Define WASM32.
+ * doc/as.texinfo: Add WebAssembly entries.
+ * NEWS: Mention the new support.
+ * Makefile.in: Regenerate.
+ * po/gas.pot: Regenerate.
+ * po/POTFILES.in: Regenerate.
+ * testsuite/gas/wasm32: New directory.
+ * testsuite/gas/wasm32/allinsn.d: New file.
+ * testsuite/gas/wasm32/allinsn.s: New file.
+ * testsuite/gas/wasm32/illegal.l: New file.
+ * testsuite/gas/wasm32/illegal.s: New file.
+ * testsuite/gas/wasm32/illegal-2.l: New file.
+ * testsuite/gas/wasm32/illegal-2.s: New file.
+ * testsuite/gas/wasm32/illegal-3.l: New file.
+ * testsuite/gas/wasm32/illegal-3.s: New file.
+ * testsuite/gas/wasm32/illegal-4.l: New file.
+ * testsuite/gas/wasm32/illegal-4.s: New file.
+ * testsuite/gas/wasm32/illegal-5.l: New file.
+ * testsuite/gas/wasm32/illegal-5.s: New file.
+ * testsuite/gas/wasm32/illegal-6.l: New file.
+ * testsuite/gas/wasm32/illegal-6.s: New file.
+ * testsuite/gas/wasm32/illegal-7.l: New file.
+ * testsuite/gas/wasm32/illegal-7.s: New file.
+ * testsuite/gas/wasm32/illegal-8.l: New file.
+ * testsuite/gas/wasm32/illegal-8.s: New file.
+ * testsuite/gas/wasm32/illegal-9.l: New file.
+ * testsuite/gas/wasm32/illegal-9.s: New file.
+ * testsuite/gas/wasm32/illegal-10.l: New file.
+ * testsuite/gas/wasm32/illegal-10.s: New file.
+ * testsuite/gas/wasm32/illegal-11.l: New file.
+ * testsuite/gas/wasm32/illegal-11.s: New file.
+ * testsuite/gas/wasm32/illegal-12.l: New file.
+ * testsuite/gas/wasm32/illegal-12.s: New file.
+ * testsuite/gas/wasm32/illegal-13.l: New file.
+ * testsuite/gas/wasm32/illegal-13.s: New file.
+ * testsuite/gas/wasm32/illegal-14.l: New file.
+ * testsuite/gas/wasm32/illegal-14.s: New file.
+ * testsuite/gas/wasm32/illegal-15.l: New file.
+ * testsuite/gas/wasm32/illegal-15.s: New file.
+ * testsuite/gas/wasm32/illegal-16.l: New file.
+ * testsuite/gas/wasm32/illegal-16.s: New file.
+ * testsuite/gas/wasm32/illegal-17.l: New file.
+ * testsuite/gas/wasm32/illegal-17.s: New file.
+ * testsuite/gas/wasm32/illegal-18.l: New file.
+ * testsuite/gas/wasm32/illegal-18.s: New file.
+ * testsuite/gas/wasm32/illegal-19.l: New file.
+ * testsuite/gas/wasm32/illegal-19.s: New file.
+ * testsuite/gas/wasm32/illegal-20.l: New file.
+ * testsuite/gas/wasm32/illegal-20.s: New file.
+ * testsuite/gas/wasm32/illegal-21.l: New file.
+ * testsuite/gas/wasm32/illegal-21.s: New file.
+ * testsuite/gas/wasm32/illegal-22.l: New file.
+ * testsuite/gas/wasm32/illegal-22.s: New file.
+ * testsuite/gas/wasm32/illegal-24.l: New file.
+ * testsuite/gas/wasm32/illegal-24.s: New file.
+ * testsuite/gas/wasm32/illegal-25.l: New file.
+ * testsuite/gas/wasm32/illegal-25.s: New file.
+ * testsuite/gas/wasm32/reloc.d: New file.
+ * testsuite/gas/wasm32/reloc.s: New file.
+ * testsuite/gas/wasm32/wasm32.exp: New tests for WebAssembly
+ architecture.
+
+2017-03-29 Alan Modra <amodra@gmail.com>
+
+ * config/tc-ppc.c (md_parse_option): Reject -mraw.
+
+2017-03-27 Alan Modra <amodra@gmail.com>
+
+ PR 21303
+ * testsuite/gas/ppc/pr21303.d,
+ * testsuite/gas/ppc/pr21303.s: New test
+ * testsuite/gas/ppc/ppc.exp: Run it.
+
+2017-03-27 Rinat Zelig <rinat@mellanox.com>
+
+ * testsuite/gas/arc/nps400-12.s: New file.
+ * testsuite/gas/arc/nps400-12.d: New file.
+
+2017-03-24 Thomas preud'homme <thomas.preudhomme@arm.com>
+
+ * config/tc-arm.: (md_begin): Set selected_cpu from *mcpu_cpu_opt when
+ CPU_DEFAULT is defined.
+
+2017-03-21 Palmer Dabbbelt <palmer@dabbelt.com>
+
+ * config/tc-riscv.c (md_show_usage): Remode defuct -m32, -m64,
+ -msoft-float, -mhard-float, -mno-rvc, and -mrvc options; and don't
+ print an invalid default ISA string.
+ * doc/c-riscv.texi (OPTIONS): Add -fpic and -fno-pic options.
+
+2017-03-22 Max Filippov <jcmvbkbc@gmail.com>
+
+ * config/tc-xtensa.c (xtensa_relax_frag): Change fx_size of the
+ reassigned fixup to size of jump instruction (3) and fx_r_type
+ to BFD_RELOC_XTENSA_SLOT0_OP, as there's only one slot.
+ (add_jump_to_trampoline): Search
+ origfrag->tc_frag_data.slot_symbols for the slot with non-NULL
+ symbol and use that slot instead of slot 0.
+
+2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
+
+ * config/tc-s390.c (s390_parse_cpu): Remove S390_INSTR_FLAG_VX2
+ from cpu_table. Remove vx2, and novx2 from cpu_flags.
+
+2017-03-21 Rinat Zelig <rinat@mellanox.com>
+
+ * testsuite/gas/arc/nps400-11.s: New file.
+ * testsuite/gas/arc/nps400-11.d: New file.
+
+2017-03-20 Nick Clifton <nickc@redhat.com>
+
+ * doc/as.texinfo (2byte): Note that if no expressions are present
+ the directive does nothing. Emphasize that the output is
+ unaligned, and that this can have an effect on the relocations
+ generated.
+ (4byte): Simplify description. Refer back to the 2byte
+ description.
+ (8byte): Likewise.
+
+2017-03-20 Richard Earnshaw <rearnsha@arm.com>
+
+ * config/tc-arm.c (arm_fpus): Note entires that should not be
+ documented.
+ * doc/c-arm.texi (-mfpu): Add missing FPU entries for neon-vfpv3 and
+ neon-fp16. Fix spelling error.
+
+2017-03-20 Richard Earnshaw <rearnsha@arm.com>
+
+ * config/tc-arm.c (arm_fpus): Add neon-vfpv3 as an alias for neon.
+
+2017-03-16 Rinat Zelig <rinat@mellanox.com>
+
+ * config/tc-arc.c (assemble_insn): Only handle ".t" and ".nt"
+ specially for ARCv2.
+
+2017-03-14 Kito Cheng <kito.cheng@gmail.com>
+
+ * config/tc-riscv.c (validate_riscv_insn): Add 'o' RVC immediate
+ encoding format, which can accept 0-valued immediates.
+ (riscv_ip): Likewise.
+
+2017-03-15 Nick Clifton <nickc@redhat.com>
+
+ * config/tc-riscv.c (riscv_pre_output_hook): Fix compile time
+ warning about discarding a const qualifier.
+
2017-03-02 Kuan-Lin Chen <rufus@andestech.com>
* config/tc-riscv.h (HWARD2_USE_FIXED_ADVANCE_PC): New define.
projects / deliverable / binutils-gdb.git / blobdiff