+2019-03-21 Alan Modra <amodra@gmail.com>
+
+ * emul.h (struct emulation): Delete strip_underscore.
+ * emul-target.h (emul_strip_underscore): Don't define.
+ (emul_struct_name): Update initialization.
+
+2019-03-21 Alan Modra <amodra@gmail.com>
+
+ * config/tc-d10v.c (md_apply_fix): Apply BFD_RELOC_8.
+ * config/tc-pdp11.c (md_apply_fix): Likewise.
+ * config/tc-d30v.c (md_apply_fix): Don't emit errors for BFD_RELOC_8,
+ BFD_RELOC_16, and BFD_RELOC_64.
+ * testsuite/gas/all/gas.exp: Move target exclusions for forward
+ test, but not cr16, to..
+ * testsuite/gas/all/forward.d: ..here, with explanation. Remove
+ d10v, d30v, and pdp11 xfails.
+
+2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (optimize_encoding): Don't check AVX for
+ EVEX vector load/store optimization. Check both operands for
+ ZMM register. Update EVEX vector load/store opcode check.
+ Choose EVEX Disp8 over VEX Disp32.
+ * testsuite/gas/i386/optimize-1.d: Updated.
+ * testsuite/gas/i386/optimize-1a.d: Likewise.
+ * testsuite/gas/i386/optimize-2.d: Likewise.
+ * testsuite/gas/i386/optimize-4.d: Likewise.
+ * testsuite/gas/i386/optimize-5.d: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-2.d: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-2a.d: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-2b.d: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-3.d: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-5.d: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-6.d: Likewise.
+ * testsuite/gas/i386/optimize-1.s: Add ZMM register load
+ test.
+ * testsuite/gas/i386/x86-64-optimize-2.s: Likewise.
+
+2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/24352
+ * config/tc-i386.c (optimize_encoding): Check only
+ cpu_arch_flags.bitfield.cpuavx512vl.
+ * testsuite/gas/i386/i386.exp: Run x86-64-optimize-2b.
+ * testsuite/gas/i386/x86-64-optimize-2.d: Revert the last
+ change.
+ * testsuite/gas/i386/x86-64-optimize-2b.d: New file.
+ * testsuite/gas/i386/x86-64-optimize-2b.s: Likewise.
+
+2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/24359
+ * testsuite/gas/i386/i386.exp: Change optimize-6a, optimize-7,
+ x86-64-optimize-7a and x86-64-optimize-8 tests to run_list_test.
+ Remove optimize-6c and x86-64-optimize-7c tests.
+ * testsuite/gas/i386/noavx-3.l: Updated.
+ * testsuite/gas/i386/noavx-4.d: Likewise.
+ * testsuite/gas/i386/noavx-5.d: Likewise.
+ * testsuite/gas/i386/noavx-3.s: Add AVX512F tests.
+ * testsuite/gas/i386/noavx-4.s: Remove AVX512F tests.
+ * testsuite/gas/i386/nosse-5.s: Likewise.
+ * testsuite/gas/i386/optimize-6a.d: Removed.
+ * testsuite/gas/i386/optimize-6c.d: Likewise.
+ * testsuite/gas/i386/optimize-7.d: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-7a.d: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-7c.d: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-8.d: Likewise.
+ * testsuite/gas/i386/optimize-6a.l: New file.
+ * testsuite/gas/i386/optimize-6a.s: Likewise.
+ * testsuite/gas/i386/optimize-7.l: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-7a.l: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-7a.s: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-8.l: Likewise.
+
+2019-03-18 Alan Modra <amodra@gmail.com>
+
+ * config/m68k-parse.y (yylex): Use temp_ilp and restore_ilp.
+ * as.c (macro_expr): Likewise.
+ * macro.c (buffer_and_nest): Likewise.
+ * read.c (temp_ilp): Remove FIXME.
+
+2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
+
+ * testsuite/gas/i386/att-regs.d: Pass -O0 to assembler.
+ * testsuite/gas/i386/avx512bw-intel.d: Likewise.
+ * testsuite/gas/i386/avx512bw.d: Likewise.
+ * testsuite/gas/i386/avx512f-intel.d: Likewise.
+ * testsuite/gas/i386/avx512f.d: Likewise.
+ * testsuite/gas/i386/disp32.d: Likewise.
+ * testsuite/gas/i386/intel-regs.d: Likewise.
+ * testsuite/gas/i386/pseudos.d: Likewise.
+ * testsuite/gas/i386/x86-64-disp32.d: Likewise.
+ * testsuite/gas/i386/x86-64-pseudos.d: Likewise.
+
+2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/24348
+ * config/tc-i386.c (optimize_encoding): Encode 128-bit and
+ 256-bit EVEX vector register load/store instructions as VEX
+ vector register load/store instructions for -O1.
+ * doc/c-i386.texi: Update -O1 documentation.
+ * testsuite/gas/i386/i386.exp: Run PR gas/24348 tests.
+ * testsuite/gas/i386/optimize-1.s: Add tests for EVEX vector
+ load/store instructions.
+ * testsuite/gas/i386/optimize-2.s: Likewise.
+ * testsuite/gas/i386/optimize-3.s: Likewise.
+ * testsuite/gas/i386/optimize-5.s: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-2.s: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-3.s: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-4.s: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-5.s: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-6.s: Likewise.
+ * testsuite/gas/i386/optimize-1.d: Updated.
+ * testsuite/gas/i386/optimize-2.d: Likewise.
+ * testsuite/gas/i386/optimize-3.d: Likewise.
+ * testsuite/gas/i386/optimize-4.d: Likewise.
+ * testsuite/gas/i386/optimize-5.d: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-2.d: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-3.d: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-4.d: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-5.d: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-6.d: Likewise.
+ * testsuite/gas/i386/optimize-7.d: New file.
+ * testsuite/gas/i386/optimize-7.s: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-8.d: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-8.s: Likewise.
+
+2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (optimize_encoding): Encode 256-bit/512-bit
+ VEX/EVEX vector register clearing instructions with 128-bit VEX
+ vector register clearing instructions at -O1.
+ * doc/c-i386.texi: Update -O1 and -O2 documentation.
+ * testsuite/gas/i386/i386.exp: Run optimize-1a and
+ x86-64-optimize-2a.
+ * testsuite/gas/i386/optimize-1a.d: New file.
+ * testsuite/gas/i386/x86-64-optimize-2a.d: Likewise.
+
+2019-03-17 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/24353
+ * config/tc-i386.c: Include <limits.h> if it exists and try
+ including <sys/param.h> if we have it.
+ (INT_MAX): Define if not defined.
+ (md_parse_option): Set optimize to INT_MAX for -Os.
+ * testsuite/gas/i386/optimize-2.s: Add a test.
+ * testsuite/gas/i386/x86-64-optimize-3.s: Likewise.
+ * testsuite/gas/i386/optimize-2.d: Updated.
+ * testsuite/gas/i386/x86-64-optimize-3.d: Likewise.
+
+2019-03-17 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/24352
+ * config/tc-i386.c (optimize_encoding): Encode 512-bit EVEX
+ with 128-bit VEX encoding only when AVX is enabled and with
+ 128-bit EVEX encoding only when AVX512VL is enabled.
+ * testsuite/gas/i386/i386.exp: Run PR gas/24352 tests.
+ * testsuite/gas/i386/optimize-6.s: New file.
+ * testsuite/gas/i386/optimize-6a.d: Likewise.
+ * testsuite/gas/i386/optimize-6b.d: Likewise.
+ * testsuite/gas/i386/optimize-6c.d: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-7.s: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-7a.d: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-7b.d: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-7c.d: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-2.d: Updated.
+
+2019-03-15 Li Hao <li.hao296@zte.com.cn>
+
+ PR 24308
+ * config/tc-i386.c (parse_insn): Check mnemp before using it to
+ determine if a suffix can be trimmed.
+
+2019-03-13 Christian Eggers <ceggers@gmx.de>
+
+ * dwarf2dbg.c (out_set_addr): Align relocation within .debug_line.
+
+2019-03-13 Christian Eggers <ceggers@gmx.de>
+
+ * dwarf2dbg.c (out_debug_line): Pad size of .debug_line section.
+
+2019-03-13 Christian Eggers <ceggers@gmx.de>
+
+ * dwarf2dbg.c (out_debug_str): Use octets for .debug_string pointers.
+
+2019-03-13 Christian Eggers <ceggers@gmx.de>
+
+ * dwarf2dbg.c (out_debug_line): Use octets for .debug_line prologue.
+
+2019-03-13 Christian Eggers <ceggers@gmx.de>
+
+ * dwarf2dbg.c (out_debug_line): Use octets for dwarf2 headers.
+ (out_debug_aranges, out_debug_info): Likewise.
+
+2019-03-13 Christian Eggers <ceggers@gmx.de>
+
+ * symbols.h (symbol_temp_new_now_octets): Declare.
+ (symbol_set_value_now_octets, symbol_octets_p): Declare.
+ * symbols.c (struct symbol_flags): New member sy_octets.
+ (symbol_temp_new_now_octets): New function.
+ (resolve_symbol_value): Return octets instead of bytes if
+ sy_octets is set.
+ (symbol_set_value_now_octets): New function.
+ (symbol_octets_p): New function.
+
+2019-03-13 Christian Eggers <ceggers@gmx.de>
+
+ * dwarf2dbg.c (dwarf2_emit_insn): Fix calculation of line info offset.
+
+2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
+
+ * testsuite/gas/s390/zarch-arch13.s: Adjust testcase to optable changes.
+ * testsuite/gas/s390/zarch-arch13.d: Likewise.
+
+2019-02-27 Matthew Malcomson <matthew.malcomson@arm.com>
+
+ * testsuite/gas/aarch64/dotproduct.d: Use multiple "as" lines.
+ * testsuite/gas/aarch64/dotproduct_armv8_4.d: Remove.
+ * testsuite/gas/aarch64/dotproduct_armv8_4.s: Remove.
+ * testsuite/gas/aarch64/illegal-dotproduct.d: Use multiple "as"
+ lines.
+ * testsuite/gas/aarch64/ldst-rcpc-armv8_2.d: Remove.
+ * testsuite/gas/aarch64/ldst-rcpc.d: Use multiple "as" lines.
+
+2019-02-24 Alan Modra <amodra@gmail.com>
+
+ * config/tc-ppc.c (parse_tls_arg): Wrap in #ifdef OBJ_ELF.
+
+2019-02-24 Alan Modra <amodra@gmail.com>
+
+ PR 24144
+ * config/obj-aout.c (obj_aout_frob_file_before_fix): Write to end
+ of section to ensure file contents cover aligned section size.
+
+2019-02-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
+
+ * config/tc-arm.c (arm_cpus): Add neoverse-n1.
+ * doc/c-arm.texi (-mcpu): Document neoverse-n1 value.
+
+2019-02-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
+
+ * config/tc-aarch64.c (aarch64_cpus): Add neoverse-e1.
+ * doc/c-aarch64.texi (-mcpu): Document neoverse-e1 value.
+
+2019-02-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
+
+ * config/tc-aarch64.c (aarch64_cpus): Add neoverse-n1.
+ * doc/c-aarch64.texi (-mcpu): Document neoverse-n1 value.
+
+2019-02-19 Paul Hua <paul.hua.gm@gmail.com>
+
+ * NEWS: Mention -m[no-]fix-loongson3-llsc.
+ * configure.ac: Add --enable-mips-fix-loongson3-llsc.
+ Define DEFAULT_MIPS_FIX_LOONGSON3_LLSC.
+ * config.in: Regenerated.
+ * configure: Likewise.
+ * config/tc-mips.c (sync_insn, mips_fix_loongson3_llsc):
+ New variables.
+ (options): New OPTION_FIX_LOONGSON3_LLSC,
+ OPTION_NO_FIX_LOONGSON3_LLSC.
+ (md_longopts): Add -m[no-]fix-loongson3-llsc.
+ (md_begin): Initialize sync insn.
+ (fix_loongson3_llsc): New.
+ (append_insn): Call fix_loongson3_llsc.
+ (md_parse_option): Handle OPTION_FIX_LOONGSON3_LLSC,
+ OPTION_NO_FIX_LOONGSON3_LLSC.
+ (md_show_usage): Display -m[no-]fix-loongson3-llsc.
+ * doc/c-mips.texi: Document -m[no-]fix-loongson3-llsc,
+ --enable-mips-fix-loongson3-llsc=[yes|no].
+
+2019-02-10 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/24165
+ * frags.c (frag_var_init): Pass max_chars to TC_FRAG_INIT as
+ max_bytes.
+ * config/tc-aarch64.h (TC_FRAG_INIT): Add and pass max_bytes to
+ aarch64_init_frag.
+ * /config/tc-arm.h (TC_FRAG_INIT): And and pass max_bytes to
+ arm_init_frag.
+ * config/tc-avr.h (TC_FRAG_INIT): And and ignore max_bytes.
+ * config/tc-ia64.h (TC_FRAG_INIT): Likewise.
+ * config/tc-mmix.h (TC_FRAG_INIT): Likewise.
+ * config/tc-nds32.h (TC_FRAG_INIT): Likewise.
+ * config/tc-ns32k.h (TC_FRAG_INIT): Likewise.
+ * config/tc-rl78.h (TC_FRAG_INIT): Likewise.
+ * config/tc-rx.h (TC_FRAG_INIT): Likewise.
+ * config/tc-score.h (TC_FRAG_INIT): Likewise.
+ * config/tc-tic54x.h (TC_FRAG_INIT): Likewise.
+ * config/tc-tic6x.h (TC_FRAG_INIT): Likewise.
+ * config/tc-xtensa.h (TC_FRAG_INIT): Likewise.
+ * config/tc-i386.h (MAX_MEM_FOR_RS_ALIGN_CODE): Set to
+ (alignment ? ((1 << alignment) - 1) : 1)
+ (i386_tc_frag_data): Add max_bytes.
+ (TC_FRAG_INIT): Add and track max_bytes.
+ (HANDLE_ALIGN): Replace MAX_MEM_FOR_RS_ALIGN_CODE with
+ fragP->tc_frag_data.max_bytes.
+ * doc/internals.texi: Update TC_FRAG_TYPE with max_bytes.
+
+2019-02-08 Jim Wilson <jimw@sifive.com>
+
+ * config/tc-riscv.c (validate_riscv_insn) <'C'>: Add 'z' support.
+ (riscv_ip) <'C'>: Add 'z' support.
+
2019-02-07 Tamar Christina <tamar.christina@arm.com>
* config/tc-arm.c (insns): Redefine THUMB_VARIANT and ARM_VARIANT for
projects / deliverable / binutils-gdb.git / blobdiff