+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/tc-aarch64.c (print_operands): Print spaces between
+ operands.
+ * testsuite/gas/aarch64/ilp32-basic.d: Expect spaces after ","
+ in addresses.
+ * testsuite/gas/aarch64/ldst-reg-imm-post-ind.d: Likewise.
+ * testsuite/gas/aarch64/ldst-reg-imm-pre-ind.d: Likewise.
+ * testsuite/gas/aarch64/ldst-reg-pair.d: Likewise.
+ * testsuite/gas/aarch64/ldst-reg-reg-offset.d: Likewise.
+ * testsuite/gas/aarch64/ldst-reg-uns-imm.d: Likewise.
+ * testsuite/gas/aarch64/ldst-reg-unscaled-imm.d: Likewise.
+ * testsuite/gas/aarch64/reloc-insn.d: Likewise.
+ * testsuite/gas/aarch64/sve.d: Likewise.
+ * testsuite/gas/aarch64/symbol.d: Likewise.
+ * testsuite/gas/aarch64/system.d: Likewise.
+ * testsuite/gas/aarch64/tls-desc.d: Likewise.
+ * testsuite/gas/aarch64/sve-invalid.l: Expect spaces after ","
+ in suggested alternatives.
+ * testsuite/gas/aarch64/verbose-error.l: Likewise.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/tc-aarch64.c (output_operand_error_record): Use "must be"
+ rather than "should be" or "expected to be" in error messages.
+ (parse_operands): Likewise.
+ * testsuite/gas/aarch64/diagnostic.l: Likewise.
+ * testsuite/gas/aarch64/legacy_reg_names.l: Likewise.
+ * testsuite/gas/aarch64/sve-invalid.l: Likewise.
+ * testsuite/gas/aarch64/sve-reg-diagnostic.l: Likewise.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/tc-aarch64.c (opcode_lookup): Search for the end of
+ a condition name, rather than assuming that it will have exactly
+ 2 characters.
+ (parse_operands): Likewise.
+ * testsuite/gas/aarch64/alias.d: Add new condition-code comments
+ to the expected output.
+ * testsuite/gas/aarch64/beq_1.d: Likewise.
+ * testsuite/gas/aarch64/float-fp16.d: Likewise.
+ * testsuite/gas/aarch64/int-insns.d: Likewise.
+ * testsuite/gas/aarch64/no-aliases.d: Likewise.
+ * testsuite/gas/aarch64/programmer-friendly.d: Likewise.
+ * testsuite/gas/aarch64/reloc-insn.d: Likewise.
+ * testsuite/gas/aarch64/b_c_1.d, testsuite/gas/aarch64/b_c_1.s:
+ New test.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * testsuite/gas/aarch64/diagnostic.s,
+ testsuite/gas/aarch64/diagnostic.l: Add tests for
+ invalid uses of MUL VL and MUL in base AArch64 instructions.
+ * testsuite/gas/aarch64/sve-add.s, testsuite/gas/aarch64/sve-add.d,
+ testsuite/gas/aarch64/sve-dup.s, testsuite/gas/aarch64/sve-dup.d,
+ testsuite/gas/aarch64/sve-invalid.s,
+ testsuite/gas/aarch64/sve-invalid.d,
+ testsuite/gas/aarch64/sve-invalid.l,
+ testsuite/gas/aarch64/sve-reg-diagnostic.s,
+ testsuite/gas/aarch64/sve-reg-diagnostic.d,
+ testsuite/gas/aarch64/sve-reg-diagnostic.l,
+ testsuite/gas/aarch64/sve.s, testsuite/gas/aarch64/sve.d: New tests.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * doc/c-aarch64.texi: Document the "sve" feature.
+ * config/tc-aarch64.c (REG_TYPE_R_Z_BHSDQ_VZP): New register type.
+ (get_reg_expected_msg): Handle it.
+ (parse_operands): When parsing operands of an SVE instruction,
+ disallow immediates that match REG_TYPE_R_Z_BHSDQ_VZP.
+ (aarch64_features): Add an entry for SVE.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/tc-aarch64.c (parse_operands): Handle the new SVE core
+ and FP register operands.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/tc-aarch64.c (double_precision_operand_p): New function.
+ (parse_operands): Use it to calculate the dp_p input to
+ parse_aarch64_imm_float. Handle the new SVE FP immediate operands.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/tc-aarch64.c (parse_operands): Handle the new SVE integer
+ immediate operands.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/tc-aarch64.c (SHIFTED_NONE, SHIFTED_MUL_VL): New
+ parse_shift_modes.
+ (parse_shift): Handle SHIFTED_MUL_VL.
+ (parse_address_main): Add an imm_shift_mode parameter.
+ (parse_address, parse_sve_address): Update accordingly.
+ (parse_operands): Handle MUL VL addressing modes.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/tc-aarch64.c (REG_TYPE_SVE_BASE, REG_TYPE_SVE_OFFSET): New
+ register types.
+ (get_reg_expected_msg): Handle them.
+ (aarch64_addr_reg_parse): New function, split out from
+ aarch64_reg_parse_32_64. Handle Z registers too.
+ (aarch64_reg_parse_32_64): Call it.
+ (parse_address_main): Add base_qualifier, offset_qualifier,
+ base_type and offset_type parameters. Handle SVE base and offset
+ registers.
+ (parse_address): Update call to parse_address_main.
+ (parse_sve_address): New function.
+ (parse_operands): Parse the new SVE address operands.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/tc-aarch64.c (SHIFTED_MUL): New parse_shift_mode.
+ (parse_shift): Handle it. Reject AARCH64_MOD_MUL for all other
+ shift modes. Skip range tests for AARCH64_MOD_MUL.
+ (process_omitted_operand): Handle AARCH64_OPND_SVE_PATTERN_SCALED.
+ (parse_operands): Likewise.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/tc-aarch64.c (parse_enum_string): New function.
+ (po_enum_or_fail): New macro.
+ (parse_operands): Handle AARCH64_OPND_SVE_PATTERN and
+ AARCH64_OPND_SVE_PRFOP.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/tc-aarch64.c (vector_el_type): Add NT_zero and NT_merge.
+ (parse_vector_type_for_operand): Assert that the skipped character
+ is a '.'.
+ (parse_predication_for_operand): New function.
+ (parse_typed_reg): Parse /z and /m suffixes for predicate registers.
+ (vectype_to_qualifier): Handle NT_zero and NT_merge.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/tc-aarch64.c (NTA_HASVARWIDTH): New macro.
+ (AARCH64_REG_TYPES): Add ZN and PN.
+ (get_reg_expected_msg): Handle them.
+ (parse_vector_type_for_operand): Add a reg_type parameter.
+ Skip the width for Zn and Pn registers.
+ (parse_typed_reg): Extend vector handling to Zn and Pn. Update the
+ call to parse_vector_type_for_operand. Set HASVARTYPE for Zn and Pn,
+ expecting the width to be 0.
+ (parse_vector_reg_list): Restrict error about [BHSD]nn operands to
+ REG_TYPE_VN.
+ (vectype_to_qualifier): Use S_[BHSD] qualifiers for NTA_HASVARWIDTH.
+ (parse_operands): Handle the new Zn and Pn operands.
+ (REGSET16): New macro, split out from...
+ (REGSET31): ...here.
+ (reg_names): Add Zn and Pn entries.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/tc-aarch64.c (output_operand_error_record): Handle
+ AARCH64_OPDE_UNTIED_OPERAND.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/tc-aarch64.c (find_best_match): Simplify, allowing an
+ instruction with all-NIL qualifiers to fail to match.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/tc-aarch64.c (parse_address_main): Remove reloc and
+ accept_reg_post_index parameters. Parse relocations and register
+ post indexes unconditionally.
+ (parse_address): Remove accept_reg_post_index parameter.
+ Update call to parse_address_main.
+ (parse_address_reloc): Delete.
+ (parse_operands): Call parse_address instead of parse_address_main.
+ Update existing callers of parse_address and make them check
+ inst.reloc.type where appropriate.
+ * testsuite/gas/aarch64/diagnostic.s: Add tests for relocations
+ in ADDR_SIMPLE, SIMD_ADDR_SIMPLE, ADDR_SIMM7 and ADDR_SIMM9 addresses.
+ Also test for invalid uses of post-index register addressing.
+ * testsuite/gas/aarch64/diagnostic.l: Update accordingly.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/tc-aarch64.c (REG_TYPE_R_Z, REG_TYPE_R_SP): New register
+ types.
+ (get_reg_expected_msg): Handle them and REG_TYPE_R64_SP.
+ (aarch64_check_reg_type): Simplify.
+ (aarch64_reg_parse_32_64): Return the reg_entry instead of the
+ register number. Return the type as a qualifier rather than an
+ "isreg32" boolean. Remove reject_sp, reject_rz and isregzero
+ parameters.
+ (parse_shifter_operand): Update call to aarch64_parse_32_64_reg.
+ Use get_reg_expected_msg.
+ (parse_address_main): Likewise. Use aarch64_check_reg_type.
+ (po_int_reg_or_fail): Replace reject_sp and reject_rz parameters
+ with a reg_type parameter. Update call to aarch64_parse_32_64_reg.
+ Use aarch64_check_reg_type to test the result.
+ (parse_operands): Update after the above changes. Parse ADDR_SIMPLE
+ addresses normally before enforcing the syntax restrictions.
+ * testsuite/gas/aarch64/diagnostic.s: Add tests for a post-index
+ zero register and for a stack pointer index.
+ * testsuite/gas/aarch64/diagnostic.l: Update accordingly.
+ Also update existing diagnostic messages after the above changes.
+ * testsuite/gas/aarch64/illegal-lse.l: Update the error message
+ for 32-bit register bases.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/tc-aarch64.c (parse_aarch64_imm_float): Remove range check.
+ (parse_operands): Check the range of 8-bit FP immediates here instead.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/tc-aarch64.c (parse_aarch64_imm_float): Report a specific
+ low-severity error for registers.
+ (parse_operands): Report an invalid floating point constant for
+ if parsing an FPIMM8 fails, and if no better error has been
+ recorded.
+ * testsuite/gas/aarch64/diagnostic.s,
+ testsuite/gas/aarch64/diagnostic.l: Add tests for integer operands
+ to FMOV.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/tc-aarch64.c (aarch64_double_precision_fmovable): Rename
+ to...
+ (can_convert_double_to_float): ...this. Accept any double-precision
+ value that converts to single precision without loss of precision.
+ (parse_aarch64_imm_float): Update accordingly.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/tc-aarch64.c (parse_immediate_expression): Add a
+ reg_type parameter.
+ (parse_constant_immediate): Likewise, and update calls.
+ (parse_aarch64_imm_float): Likewise.
+ (parse_big_immediate): Likewise.
+ (po_imm_nc_or_fail): Update accordingly, passing down a new
+ imm_reg_type variable.
+ (po_imm_of_fail): Likewise.
+ (parse_operands): Likewise.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/tc-aarch64.c (parse_neon_reg_list): Rename to...
+ (parse_vector_reg_list): ...this and take a register type
+ as input.
+ (parse_operands): Update accordingly.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/tc-aarch64.c (parse_neon_type_for_operand): Rename to...
+ (parse_vector_type_for_operand): ...this.
+ (parse_typed_reg): Update accordingly.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/tc-aarch64.c (neon_type_el): Rename to...
+ (vector_type_el): ...this.
+ (parse_neon_type_for_operand): Update accordingly.
+ (parse_typed_reg): Likewise.
+ (aarch64_reg_parse): Likewise.
+ (vectype_to_qualifier): Likewise.
+ (parse_operands): Likewise.
+ (eq_neon_type_el): Likewise. Rename to...
+ (eq_vector_type_el): ...this.
+ (parse_neon_reg_list): Update accordingly.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/tc-aarch64.c (neon_el_type: Rename to...
+ (vector_el_type): ...this.
+ (neon_type_el): Update accordingly.
+ (parse_neon_type_for_operand): Likewise.
+ (vectype_to_qualifier): Likewise.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/tc-aarch64.c (parse_neon_operand_type): Delete.
+ (parse_typed_reg): Call parse_neon_type_for_operand directly.
+
+2016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * testsuite/gas/arc/textinsnxop.d: New file.
+ * testsuite/gas/arc/textinsnxop.s: Likewise.
+
+2016-09-15 Jose E. Marchesi <jose.marchesi@oracle.com>
+
+ * testsuite/gas/sparc/sparc.exp (gas_64_check): Run
+ dcti-couples-v9 only in ELF targets to avoid spurious failures in
+ sparc-aout and sparc-coff targets.
+
+2016-09-14 Peter Bergner <bergner@vnet.ibm.com>
+
+ * testsuite/gas/ppc/power9.d <slbiag, cpabort> New tests.
+ <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
+ xor3, cp_abort, copy_first, paste, paste_last, sync>: Remove tests.
+ <copy, paste.>: Update tests.
+ * testsuite/gas/ppc/power9.s: Likewise.
+
+2016-09-14 Jose E. Marchesi <jose.marchesi@oracle.com>
+
+ * config/tc-sparc.c (sparc_ip): Print the instruction arguments
+ in "architecture mismatch" error messages.
+
+2016-09-14 Jose E. Marchesi <jose.marchesi@oracle.com>
+
+ * config/tc-sparc.c (md_assemble): Detect and warning on
+ unpredictable DCTI couples in certain arches.
+ (dcti_couples_detect): New global.
+ (md_longopts): Add command line option -dcti-couples-detect.
+ (md_show_usage): Document -dcti-couples-detect.
+ (md_parse_option): Handle OPTION_DCTI_COUPLES_DETECT.
+ * testsuite/gas/sparc/sparc.exp (gas_64_check): Run
+ dcti-couples-v8, dcti-couples-v9 and dcti-couples-v9c tests.
+ * testsuite/gas/sparc/dcti-couples.s: New file.
+ * testsuite/gas/sparc/dcti-couples-v9c.d: Likewise.
+ * testsuite/gas/sparc/dcti-couples-v8.d: Likewise.
+ * testsuite/gas/sparc/dcti-couples-v9.d: Likewise.
+ * testsuite/gas/sparc/dcti-couples-v9c.l: Likewise.
+ * testsuite/gas/sparc/dcti-couples-v8.l: Likewise.
+ * doc/as.texinfo (Overview): Document --dcti-couples-detect.
+ * doc/c-sparc.texi (Sparc-Opts): Likewise.
+
+2016-09-14 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * testsuite/gas/arc/tls-relocs2.d: New file.
+ * testsuite/gas/arc/tls-relocs2.s: Likewise.
+ * config/tc-arc.c (tokenize_arguments): Accept offsets when base
+ is used.
+
+2016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
+
+ * config/tc-s390.c (s390_parse_cpu): Support alternate arch
+ strings.
+ * doc/as.texinfo: Document new arch strings.
+ * doc/c-s390.texi: Likewise.
+
+2016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
+
+ * config/tc-s390.c: Set all facitily bits by default
+
+2016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
+
+ * testsuite/gas/s390/zarch-z196.d: Adjust testcase.
+
+2016-09-08 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (i386_target_format): Allow PROCESSOR_IAMCU
+ for Intel MCU.
+
+2016-09-07 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (valid_iamcu_cpu_flags): Removed.
+ (set_cpu_arch): Updated.
+ (md_parse_option): Likewise.
+ * testsuite/gas/i386/i386.exp: Run iamcu-4 and iamcu-5. Remove
+ iamcu-inval-2 and iamcu-inval-3.
+ * testsuite/gas/i386/iamcu-4.d: New file.
+ * testsuite/gas/i386/iamcu-4.s: Likewise.
+ * testsuite/gas/i386/iamcu-5.d: Likewise.
+ * testsuite/gas/i386/iamcu-5.s: Likewise.
+ * testsuite/gas/i386/iamcu-inval-2.l: Removed.
+ * testsuite/gas/i386/iamcu-inval-2.s: Likewise.
+ * testsuite/gas/i386/iamcu-inval-3.l: Likewise.
+ * testsuite/gas/i386/iamcu-inval-3.s: Likewise.
+
+2016-09-07 Richard Earnshaw <rearnsha@arm.com>
+
+ * config/tc-arm.c ((arm_cpus): Use ARM_ARCH_V8A_CRC for all
+ ARMv8-A CPUs except xgene1.
+
+2016-08-31 Alan Modra <amodra@gmail.com>
+
+ * config/tc-ppc.c (md_assemble): Set sh_flags for VLE. Test
+ ppc_cpu rather than calling ppc_mach to determine VLE mode.
+ (ppc_frag_check, ppc_handle_align): Likewise use ppc_cpu.
+
+2016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
+
+ * testsuite/gas/sparc/crypto.d: Rename invalid opcode camellia_fi
+ to camellia_fl.
+ * testsuite/gas/sparc/crypto.s: Likewise.
+
+2016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * config/tc-arm.c (v7m_psrs): Add MSPLIM, PSPLIM, MSPLIM_NS,
+ PSPLIM_NS, PRIMASK_NS, BASEPRI_NS, FAULTMASK_NS, CONTROL_NS, SP_NS and
+ their lowecase counterpart special registers. Write register
+ identifier in hex.
+ * testsuite/gas/arm/archv8m-cmse-msr.s: Reorganize tests per
+ operation, special register and then case. Use different register for
+ each operation. Add tests for new special registers.
+ * testsuite/gas/arm/archv8m-cmse-msr-base.d: Adapt expected result
+ accordingly.
+ * testsuite/gas/arm/archv8m-cmse-msr-main.d: Likewise.
+ * testsuite/gas/arm/archv8m-main-dsp-4.d: Likewise.
+
+2016-08-25 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * config/tc-arm.c (v7m_psrs): Remove msp_s, MSP_S, psp_s and PSP_S
+ special registers.
+ * testsuite/gas/arm/archv8m-cmse-msr.s: Remove test for above special
+ registers.
+ * testsuite/gas/arm/archv8m-cmse-msr-base.d: Likewise.
+ * testsuite/gas/arm/archv8m-cmse-msr-main.d: Likewise.
+ * testsuite/gas/arm/archv8m-main-dsp-4.d: Likewise.
+
+2016-08-24 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (cpu_arch): Add .ptwrite.
+ * doc/c-i386.texi: Document ptwrite and .ptwrite.
+ * testsuite/gas/i386/i386.exp: Run ptwrite, ptwrite-intel,
+ x86-64-ptwrite and x86-64-ptwrite-intel.
+ * testsuite/gas/i386/ptwrite-intel.d: New file.
+ * testsuite/gas/i386/ptwrite.d: Likewise.
+ * testsuite/gas/i386/ptwrite.s: Likewise.
+ * testsuite/gas/i386/x86-64-ptwrite-intel.d: Likewise.
+ * testsuite/gas/i386/x86-64-ptwrite.d: Likewise.
+ * testsuite/gas/i386/x86-64-ptwrite.s: Likewise.
+
+2016-08-19 Tamar Christina <tamar.christina@arm.com>
+
+ * config/tc-arm.c (do_co_reg2c): Added constraint.
+ * testsuite/gas/arm/dest-unpredictable.s: New.
+ * testsuite/gas/arm/dest-unpredictable.l: New.
+ * testsuite/gas/arm/dest-unpredictable.d: New.
+
+2016-08-19 Nick Clifton <nickc@redhat.com>
+
+ * testsuite/gas/i386/ilp32/x86-64-unwind.d: Adjust expected
+ ordering of sections.
+ * testsuite/gas/i386/x86-64-unwind.d: Likewise.
+ * testsuite/gas/ia64/alias-ilp32.d: Likewise.
+ * testsuite/gas/ia64/alias.d: Likewise.
+ * testsuite/gas/ia64/group-1.d: Likewise.
+ * testsuite/gas/ia64/group-2.d: Likewise.
+ * testsuite/gas/ia64/secname-ilp32.d: Likewise.
+ * testsuite/gas/ia64/secname.d: Likewise.
+ * testsuite/gas/ia64/unwind-ilp32.d: Likewise.
+ * testsuite/gas/ia64/unwind.d: Likewise.
+ * testsuite/gas/ia64/xdata-ilp32.d: Likewise.
+ * testsuite/gas/ia64/xdata.d: Likewise.
+ * testsuite/gas/mmix/bspec-1.d: Likewise.
+ * testsuite/gas/mmix/bspec-2.d: Likewise.
+ * testsuite/gas/mmix/byte-1.d: Likewise.
+ * testsuite/gas/mmix/loc-1.d: Likewise.
+ * testsuite/gas/mmix/loc-2.d: Likewise.
+ * testsuite/gas/mmix/loc-3.d: Likewise.
+ * testsuite/gas/mmix/loc-4.d: Likewise.
+ * testsuite/gas/mmix/loc-5.d: Likewise.
+ * testsuite/gas/tic6x/scomm-directive-4.d: Likewise.
+
+2016-08-11 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/tc-aarch64.c (parse_aarch64_imm_float): Reject -0.0.
+ * testsuite/gas/aarch64/illegal.s, testsuite/gas/aarch64/illegal.l:
+ Add tests for -0.0. Add an end-of-file comment.
+
+2016-08-05 Nick Clifton <nickc@redhat.com>
+
+ PR gas/20429
+ * config/tc-arm.c (do_vfp_nsyn_push): Check that no more than 16
+ registers are pushed.
+ (do_vfp_nsyn_pop): Check that no more than 16 registers are
+ popped.
+ * testsuite/gas/arm/pr20429.s: New test.
+ * testsuite/gas/arm/pr20429.d: New test driver.
+ * testsuite/gas/arm/pr20429.1: Expected error output.
+
+ PR gas/20364
+ * config/tc-aarch64.c (s_ltorg): Change the mapping state after
+ aligning the frag.
+ (aarch64_init): Treat rs_align frags in code sections as
+ containing code, not data.
+ * testsuite/gas/aarch64/pr20364.s: New test.
+ * testsuite/gas/aarch64/pr20364.d: New test driver.
+
+2016-08-04 Stefan Trleman <stefan.teleman@oracle.com>
+
+ PR gas/20427
+ * config/tc-sparc.c (cons_fix_new_sparc): Prevent the generation
+ of 64-bit relocation types when assembling for a 32-bit Solaris
+ target.
+
+2016-07-27 Jose E. Marchesi <jose.marchesi@oracle.com>
+
+ * testsuite/gas/sparc/sparc.exp: Use is_elf_format to discriminate
+ ELF targets.
+ Run natural, natural-32, pr4587, ticc-imm-reg, v8-movwr-imm,
+ pause, save-args, cbcond, cfr, crypto edge, flush, hpcvis3, ima,
+ ld_st_fsr, ldtw_sttw, ldd_std, ldx_stx, ldx_efsr, mwait, mcdper,
+ sparc5vis4, xcrypto, v9branch1 and imm-plus-rreg only in ELF
+ targets.
+ (sparc_elf_setup): Delete.
+ * testsuite/gas/sparc/save-args.d: Fix a copy-paste typo in the
+ test's #name entry.
+
+2016-07-27 Maciej W. Rozycki <macro@imgtec.com>
+
+ * config/tc-mips.c (RELAX_MICROMIPS_ENCODE): Add `nods' flag.
+ (RELAX_MICROMIPS_RELAX32, RELAX_MICROMIPS_TOOFAR16)
+ (RELAX_MICROMIPS_MARK_TOOFAR16, RELAX_MICROMIPS_CLEAR_TOOFAR16)
+ (RELAX_MICROMIPS_TOOFAR32, RELAX_MICROMIPS_MARK_TOOFAR32)
+ (RELAX_MICROMIPS_CLEAR_TOOFAR32): Shift bits.
+ (get_append_method): Also return APPEND_ADD_COMPACT for
+ microMIPS instructions.
+ (find_altered_mips16_opcode): Exclude macros from matching.
+ Factor code out...
+ (find_altered_opcode): ... to this new function.
+ (find_altered_micromips_opcode): New function.
+ (frag_branch_delay_slot_size): Likewise.
+ (append_insn): Handle microMIPS branch/jump compaction.
+ (macro_start): Likewise.
+ (relaxed_micromips_32bit_branch_length): Likewise.
+ (md_convert_frag): Likewise.
+ * testsuite/gas/mips/micromips.s: Add conditional explicit NOPs
+ for delay slot filling.
+ * testsuite/gas/mips/micromips-b16.s: Add explicit NOPs for
+ delay slot filling.
+ * testsuite/gas/mips/micromips-size-1.s: Likewise.
+ * testsuite/gas/mips/micromips.l: Adjust line numbers.
+ * testsuite/gas/mips/micromips-warn.l: Likewise.
+ * testsuite/gas/mips/micromips-size-1.l: Likewise.
+ * testsuite/gas/mips/micromips.d: Adjust padding.
+ * testsuite/gas/mips/micromips-trap.d: Likewise.
+ * testsuite/gas/mips/micromips-insn32.d: Likewise.
+ * testsuite/gas/mips/micromips-noinsn32.d: Likewise.
+ * testsuite/gas/mips/micromips@beq.d: Update patterns for
+ branch/jump compaction.
+ * testsuite/gas/mips/micromips@bge.d: Likewise.
+ * testsuite/gas/mips/micromips@bgeu.d: Likewise.
+ * testsuite/gas/mips/micromips@blt.d: Likewise.
+ * testsuite/gas/mips/micromips@bltu.d: Likewise.
+ * testsuite/gas/mips/micromips@branch-misc-4.d: Likewise.
+ * testsuite/gas/mips/micromips@branch-misc-4-64.d: Likewise.
+ * testsuite/gas/mips/micromips@branch-misc-5.d: Likewise.
+ * testsuite/gas/mips/micromips@branch-misc-5pic.d: Likewise.
+ * testsuite/gas/mips/micromips@branch-misc-5-64.d: Likewise.
+ * testsuite/gas/mips/micromips@branch-misc-5pic-64.d: Likewise.
+ * testsuite/gas/mips/micromips@jal-svr4pic-local.d: Likewise.
+ * testsuite/gas/mips/micromips@jal-svr4pic-local-n32.d:
+ Likewise.
+ * testsuite/gas/mips/micromips@jal-svr4pic-local-n64.d:
+ Likewise.
+ * testsuite/gas/mips/micromips@loc-swap.d: Likewise.
+ * testsuite/gas/mips/micromips@loc-swap-dis.d: Likewise.
+ * testsuite/gas/mips/micromips@relax.d: Likewise.
+ * testsuite/gas/mips/micromips@relax-at.d: Likewise.
+ * testsuite/gas/mips/micromips@relax-swap3.d: Likewise.
+ * testsuite/gas/mips/branch-extern-2.d: Likewise.
+ * testsuite/gas/mips/branch-extern-4.d: Likewise.
+ * testsuite/gas/mips/branch-section-2.d: Likewise.
+ * testsuite/gas/mips/branch-section-4.d: Likewise.
+ * testsuite/gas/mips/branch-weak-2.d: Likewise.
+ * testsuite/gas/mips/branch-weak-5.d: Likewise.
+ * testsuite/gas/mips/micromips-branch-absolute.d: Likewise.
+ * testsuite/gas/mips/micromips-branch-absolute-n32.d: Likewise.
+ * testsuite/gas/mips/micromips-branch-absolute-n64.d: Likewise.
+ * testsuite/gas/mips/micromips-branch-absolute-addend.d:
+ Likewise.
+ * testsuite/gas/mips/micromips-branch-absolute-addend-n32.d:
+ Likewise.
+ * testsuite/gas/mips/micromips-branch-absolute-addend-n64.d:
+ Likewise.
+ * testsuite/gas/mips/micromips-compact.d: New test.
+ * testsuite/gas/mips/mips.exp: Run the new test.
+
+2016-07-27 Graham Markall <graham.markall@embecosm.com>
+
+ * config/tc-arc.c: Add new global arc_addrtype_hash.
+ Define O_colon and O_addrtype.
+ (debug_exp): Add O_colon and O_addrtype.
+ (tokenize_arguments): Handle colon and address type
+ tokens.
+ (declare_addrtype): New function.
+ (md_begin): Initialise arc_addrtype_hash.
+ (arc_parse_name): Add lookup of address types.
+ (assemble_insn): Handle colons and address types by
+ ignoring them.
+ * testsuite/gas/arc/nps400-8.s: New file.
+ * testsuite/gas/arc/nps400-8.d: New file.
+ * testsuite/gas/arc/nps400-8.s: Add PMU instruction tests.
+ * testsuite/gas/arc/nps400-8.d: Add expected PMU
+ instruction output.
+
+2016-07-26 Maciej W. Rozycki <macro@imgtec.com>
+
+ * config/tc-mips.c (RELAX_MICROMIPS_ENCODE): Add `insn32' flag.
+ (RELAX_MICROMIPS_INSN32): New macro.
+ (RELAX_MICROMIPS_UNCOND, RELAX_MICROMIPS_COMPACT)
+ (RELAX_MICROMIPS_LINK, RELAX_MICROMIPS_RELAX32)
+ (RELAX_MICROMIPS_TOOFAR16, RELAX_MICROMIPS_MARK_TOOFAR16)
+ (RELAX_MICROMIPS_CLEAR_TOOFAR16, RELAX_MICROMIPS_TOOFAR32)
+ (RELAX_MICROMIPS_MARK_TOOFAR32, RELAX_MICROMIPS_CLEAR_TOOFAR32):
+ Shift bits.
+ (append_insn): Record `mips_opts.insn32' with relaxed microMIPS
+ branches.
+ (relaxed_micromips_32bit_branch_length): Handle the `insn32'
+ mode.
+ (md_convert_frag): Likewise.
+ * testsuite/gas/mips/micromips-branch-relax.s: Add `insn32'
+ conditionals.
+ * testsuite/gas/mips/micromips-branch-relax.l: Update line
+ numbers accordingly.
+ * testsuite/gas/mips/micromips-branch-relax-pic.l: Likewise.
+ * testsuite/gas/mips/micromips-branch-relax-insn32.d: New test.
+ * testsuite/gas/mips/micromips-branch-relax-insn32-pic.d: New
+ test.
+ * testsuite/gas/mips/micromips-branch-relax-insn32.l: New
+ stderr output.
+ * testsuite/gas/mips/micromips-branch-relax-insn32-pic.l: New
+ stderr output.
+ * testsuite/gas/mips/mips.exp: Run the new tests.
+
+2016-07-21 H.J. Lu <hongjiu.lu@intel.com>
+
+ * configure: Regenerated.
+
+2016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * testsuite/gas/arc/dsp.d: New file.
+ * testsuite/gas/arc/dsp.s: Likewise.
+ * testsuite/gas/arc/fpu.d: Likewise.
+ * testsuite/gas/arc/fpu.s: Likewise.
+ * testsuite/gas/arc/ext2op.d: Add specific disassembler option.
+ * testsuite/gas/arc/ext3op.d: Likewise.
+ * testsuite/gas/arc/tdpfp.d: Likewise.
+ * testsuite/gas/arc/tfpuda.d: Likewise.
+
+2016-07-20 Maciej W. Rozycki <macro@imgtec.com>
+
+ * config/tc-mips.c (mips_force_relocation): Remove
+ R_MIPS_PC26_S2 and R_MIPS_PC21_S2.
+
+2016-07-19 Maciej W. Rozycki <macro@imgtec.com>
+
+ * config/tc-mips.c (mips_force_relocation, mips_fix_adjustable):
+ Adjust comments for BAL to JALX linker conversion.
+ (fix_bad_cross_mode_branch_p): Accept cross-mode BAL.
+ * testsuite/gas/mips/unaligned-branch-1.l: Update error messages
+ expected.
+ * testsuite/gas/mips/unaligned-branch-micromips-1.l: Likewise.
+ * testsuite/gas/mips/branch-local-4.d: New test.
+ * testsuite/gas/mips/branch-local-n32-4.d: New test.
+ * testsuite/gas/mips/branch-local-n64-4.d: New test.
+ * testsuite/gas/mips/branch-addend.d: New test.
+ * testsuite/gas/mips/branch-addend-n32.d: New test.
+ * testsuite/gas/mips/branch-addend-n64.d: New test.
+ * testsuite/gas/mips/branch-local-4.s: New test source.
+ * testsuite/gas/mips/branch-addend.s: New test source.
+ * testsuite/gas/mips/mips.exp: Run the new tests.
+
2016-07-19 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (mips_force_relocation): Also retain branch
projects / deliverable / binutils-gdb.git / blobdiff