Process 64-bit imm/disp only for 64-bit BFD

[deliverable/binutils-gdb.git] / gas / ChangeLog

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 17fa42e700e2ad73dc05d2b082345eb9a41a579e..e80a36da42f25fc49649085ea42396a4610ba21e 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,8 +1,61 @@
+2015-12-18  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * config/tc-i386.c (optimize_imm): Store 32-bit immediate in
+       64-bit only for 64-bit BFD.
+       (optimize_disp): Optimize 64-bit displacement to 32-bit only
+       for 64-bit BFD.
+
+2015-12-17  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
+
+       * gas/config/tc-arm.c (aeabi_set_public_attributes): Adjust
+       TAG_ARCH_profile for armv8-a.
+       * gas/testsuite/gas/arm/armv8a-automatic-hlt.d: New test.
+       * gas/testsuite/gas/arm/armv8a-automatic-hlt.s: New test.
+       * gas/testsuite/gas/arm/armv8a-automatic-lda.d: New test.
+       * gas/testsuite/gas/arm/armv8a-automatic-lda.s: New test.
+
+2015-12-16 Mickael Guene <mickael.guene@st.com>
+
+       * doc/c-arm.texi: Add documentation about new directives
+       * config/tc-arm.c (group_reloc_table): Add mapping between gas
+       syntax and new relocations.
+       (do_t_add_sub): Keep new relocations for add operand.
+       (do_t_mov_cmp): Keep new relocations for mov operand.
+       (insns): Use 'shifter operand with possible group relocation'
+       operand parse code for movs operand.
+       (md_apply_fix): Implement mov and add encoding when new
+       relocations on them.
+       (tc_gen_reloc): Add new relocations.
+       (arm_fix_adjustable): Since offset has a limited range ([0:255])
+       we disable adjust_reloc_syms() for new relocations.
+
+2015-12-15  Nick Clifton  <nickc@redhat.com>
+
+       * doc/c-msp430.texi (MSP430 Options): Remove references to a
+       non-existant silicon errata.
+       * config/tc-msp430.c: Likewise.
+
+2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * config/tc-aarch64.c (parse_neon_type_for_operand): Adjust to
+       take into account new vector type 2H.
+       (vectype_to_qualifier): Likewise.
+
 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
 
        * config/tc-aarch64.c (vectype_to_qualifier): Calculate operand
        qualifier from per-type base and offet.
 
+2015-12-14  Yoshinori Sato <ysato@users.sourceforge.jp>
+
+       * config/rx-defs.h(rx_cpu_type): Add RXV2 type.
+       * config/tc-rx.c(cpu_type_list): New type lookup table.
+       (md_parse_option): Use lookup table for choose cpu.
+       (md_show_usage): Add rxv2 for mcpu option.
+       * doc/c-rx.texi: Likewise.
+       * config/rx-parse.y: Add v2 instructions and ACC register.
+       (rx_check_v2): check v2 type.
+
 2015-12-14  Jan Beulich  <jbeulich@suse.com>
 
        * dw2gencfi.c (dot_cfi_label): Free "name".