+2012-12-17 Nick Clifton <nickc@redhat.com>
+
+ * CONTRIBUTORS: Add copyright notice.
+ * MAINTAINERS: Likewise.
+ * Makefile.am: Likewise.
+ * NEWS: Likewise.
+ * README: Likewise.
+ * configure.com: Likewise.
+ * configure.in: Likewise.
+ * configure.tgt: Likewise.
+ * itbl-lex-wrapper.c: Likewise.
+ * makefile.vms: Likewise.
+ * config/bfin-lex-wrapper.c: Likewise.
+ * config/obj-fdpicelf.c: Likewise.
+ * config/obj-fdpicelf.h: Likewise.
+ * doc/Makefile.am: Likewise.
+ * doc/h8.texi: Likewise.
+ * Makefile.in: Regenerate.
+ * doc/Makefile.in: Regenerate.
+
+2012-12-11 Edgar E. Iglesias <edgar.iglesias@gmail.com>
+
+ * config/tc-microblaze.c: Define TLS offsets
+ (md_relax_table): Add TLS offsets
+ (imm_types), (match_imm), (get_imm_otype): New to support TLS offsets.
+ (tc_microblaze_fix_adjustable): Add TLS relocs.
+ (md_convert_frag): Support TLS offsets.
+ (md_apply_fix), (md_estimate_size_before_relax), (tc_gen_reloc):
+ Add TLS relocs
+
+2012-12-06 Yufeng Zhang <yufeng.zhang@arm.com>
+
+ * config/tc-aarch64.c (exp_has_bignum_p): Remove.
+ (my_get_expression): Not get rid of bignums.
+ (s_ltorg): Increase the range of 'align'.
+ (programmer_friendly_fixup): Allow bignum expression.
+
+2012-11-29 David Holsgrove <david.holsgrove@xilinx.com>
+
+ * config/tc-microblaze.c: Rename INST_TYPE_RD_R1_SPECIAL to
+ INST_TYPE_R1_R2_SPECIAL, don't set RD for wic.
+
+2012-11-28 Julian Brown <julian@codesourcery.com>
+
+ * config/tc-arm.c (md_apply_fix): Fix conversion of BL to BLX for
+ local targets in Thumb mode.
+
+2012-11-23 Alan Modra <amodra@gmail.com>
+
+ * config/tc-ppc.c (sticky): New var.
+ (md_parse_option, ppc_machine): Update ppc_parse_cpu calls.
+
+2012-11-21 Edgar E. Iglesias <edgar.iglesias@gmail.com>
+
+ * config/tc-microblaze.c (parse_reg): Parse REG_SLR, REG_SHR
+
+2012-11-20 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/14859
+ * gas/i386/x86-64-opcode.s: Add jecxz.
+ * gas/i386/x86-64-opcode.d: Updated.
+
+2012-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
+
+ * config/tc-aarch64.c (first_error_fmt): Add ATTRIBUTE_UNUSED to the
+ local variable "ret".
+
+2012-11-20 Roland McGrath <mcgrathr@google.com>
+
+ * config/tc-arm.c (arm_symbol_chars): New variable.
+ * config/tc-arm.h (tc_symbol_chars): New macro, defined to that.
+
+2012-11-20 David S. Miller <davem@davemloft.net>
+
+ * config/tc-sparc.c (md_parse_option): Only certain arch
+ specifications should override the object to be 32-bit
+ or 64-bit.
+
+2012-11-14 David Holsgrove <david.holsgrove@xilinx.com>
+
+ * config/tc-microblaze.c (md_assemble): Add support for INST_TYPE_IMM5
+
+2012-11-14 Ulrich Weigand <uweigand@de.ibm.com>
+
+ * config/tc-ppc.c (md_apply_fix): Leave field zero when emitting
+ an ELF reloc on data as well.
+
+2012-11-09 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * read.h (s_vendor_attribute): Move to...
+ * config/obj-elf.h (obj_elf_vendor_attribute): ... here.
+ * read.c (potable): Remove "gnu_attribute".
+ (skip_whitespace, skip_past_char, skip_past_comma): Delete, move
+ to config/obj-elf.c.
+ (s_vendor_attribute): Delete, move to obj_elf_vendor_attribute
+ in config/obj-elf.c.
+ (s_gnu_attribute): Delete, move to obj_elf_gnu_attribute in
+ config/obj-elf.c.
+ * config/obj-elf.c (elf_pseudo_table): Add "gnu_attribute".
+ (skip_whitespace, skip_past_char, skip_past_comma): New, moved
+ from read.c.
+ (obj_elf_vendor_attribute): New, moved from s_vendor_attribute
+ in read.c.
+ (obj_elf_gnu_attribute): New, moved from s_gnu_attribute in
+ read.c.
+ * config/tc-arm.c (s_arm_eabi_attribute): Rename
+ s_vendor_attribute to obj_elf_vendor_attribute.
+ * config/tc-tic6x.c (s_tic6x_c6xabi_attribute): Likewise.
+
+2012-11-09 Nick Clifton <nickc@redhat.com>
+
+ * config/obj-elf.c (obj_elf_change_section): Allow init array
+ sections to have the SHF_EXECINSTR attribute for the RX target.
+ * config/tc-rx.c (elf_flags): Initialise with E_FLAG_RX_ABI.
+ (enum options): Add OPTION_USES_GCC_ABI and OPTION_USES_RX_ABI.
+ (md_longopts): Add -mgcc-abi and -mrx-abi.
+ (md_parse_option): Add support for OPTION_USES_GCC_ABI and
+ OPTION_USES_RX_ABI.
+ * doc/as.texinfo (RX Options): Add mention of remaining RX
+ options.
+ * doc/c-rx.texi: Document -mgcc-abi and -mrx-abi.
+
+ * config/tc-v850.c (v850_target_arch): New.
+ (v850_target_format): New.
+ (set_machine): Use v850_target_arch.
+ (md_begin): Likewise.
+ (md_show_usage): Document new switches.
+ (md_parse_option): Add -mgcc-abi, -mrh850-abi, -m8byte-align and
+ -m4byte-align.
+ * config/tc-v850.c (TARGET_ARCH) Use v850_target_arch.
+ (TARGET_FORMAT): Use v850_target_format.
+ * doc/c-v850.texi: Document new options.
+
+2012-11-09 David Holsgrove <david.holsgrove@xilinx.com>
+
+ * tc-microblaze.c (md_longopts): Define OPTION_EB and
+ OPTION_EL for target.
+ (md_parse_option): Likewise.
+ * tc-microblaze.h: Set elf32-microblazeel if not
+ target_big_endian for TARGET_FORMAT.
+ * configure.tgt: Add microblazeel and set endian per target.
+
+2012-11-09 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/atof-ieee.c (gen_to_words): Remove trailing redundant
+ `;'.
+ * config/atof-vax.c (flonum_gen2vax): Likewise.
+ * config/tc-d10v.c (write_2_short): Likewise.
+ * config/tc-i386-intel.c (i386_intel_simplify): Likewise.
+ * config/tc-s390.c (tc_s390_force_relocation): Likewise.
+ * config/tc-v850.c (md_parse_option): Likewise.
+ * config/tc-xtensa.c (find_address_of_next_align_frag): Likewise.
+ * dwarf2dbg.c (out_header): Likewise.
+ * symbols.c (dollar_label_name): Likewise.
+ (fb_label_name): Likewise.
+
+2012-11-08 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * config/tc-mips.c (mips_ip) <'u'>: Default to BFD_RELOC_LO16.
+
+2012-11-08 Alan Modra <amodra@gmail.com>
+
+ * po/POTFILES.in: Regenerate.
+
+2012-11-07 James Murray <jsm@jsm-net.demon.co.uk>
+
+ * config/tc-m68hc11.c: Fix R_M68HC12_16B relocation for movb/w
+
+2012-11-07 David Holsgrove <david.holsgrove@xilinx.com>
+
+ * config/tc-microblaze.c: Remove special register condition check
+ for INST_TYPE_RFSL related instructions.
+
+2012-11-06 Alan Modra <amodra@gmail.com>
+
+ * config/tc-xgate.c: Make some functions static. Formatting
+ style and whitespace fixes. Wrap overly long lines. Format
+ help message.
+
+2012-11-06 Alan Modra <amodra@gmail.com>
+
+ * config/tc-tic4x.c: Remove alignment TODO comments.
+ (tic4x_do_align): Enable subseg_text_p test.
+
+2012-11-06 Alan Modra <amodra@gmail.com>
+
+ * config/tc-ppc.c (ppc_elf_adjust_symtab): New function, split out..
+ (ppc_frob_file_before_adjust): ..from here.
+ (md_apply_fix): Set BSF_KEEP on .TOC. if not @tocbase.
+ * config/tc-ppc.h (ppc_elf_adjust_symtab): Declare.
+ (tc_adjust_symtab): Define.
+
+2012-11-06 Alan Modra <amodra@gmail.com>
+
+ * config/tc-ppc.c (md_apply_fix): Fix xcoff build breakage from
+ last patch.
+
+2012-11-05 Sean Keys <skeys@ipdatasys.com>
+
+ * config/tc-xgate.c: Remove bogus use of <fx_pcrel_adjust>.
+ * config/tc-m68hc11.c: Likewise.
+
+2012-11-05 Alan Modra <amodra@gmail.com>
+
+ * configure.in: Apply 2012-09-10 change to config.in here.
+
+2012-11-05 Alan Modra <amodra@gmail.com>
+
+ * config/tc-ppc.c (md_chars_to_number): Delete.
+ (ppc_setup_opcodes): Assert num_powerpc_operands fit.
+ (ppc_is_toc_sym): Move earlier in file.
+ (md_assemble): Move code setting reloc from md_apply_fix. Combine
+ non-ELF code setting fixup with ELF code. Stash opindex in
+ fx_pcrel_adjust. Adjust fixup offset for VLE. Don't set
+ fx_no_overflow here.
+ (md_apply_fix): Rewrite to use ppc_insert_operand for all
+ resolved instruction fields. Leave insn field zero when
+ emitting an ELF reloc in most cases.
+
+ * write.h (struct fix <fx_pcrel_adjust>): Make it a signed char.
+ * config/tc-m68k.c (tc_gen_reloc, md_pcrel_from): Remove explicit
+ sign extendion of fx_pxrel_adjust.
+
+2012-11-01 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * config/tc-mips.c (is_delay_slot_valid): Simplify expression.
+
+2012-11-01 Chao-ying Fu <fu@mips.com>
+
+ * config/tc-mips.c (append_insn): Set fx_no_overflow for 16-bit
+ microMIPS branch relocations.
+
+2012-11-01 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * config/tc-mips.c (is_delay_slot_valid): Don't accept macros
+ in 16-bit delay slots.
+ (macro_build_jalr): Emit 32-bit JALR if placed in a 32-bit delay
+ slot.
+ (macro) <M_JAL_2>: Likewise
+
+2012-10-31 David Holsgrove <david.holsgrove@xilinx.com>
+
+ * config/tc-microblaze.c: Check for weak symbols before
+ emitting relocation.
+
+2012-10-29 Alan Modra <amodra@gmail.com>
+
+ * sb.c (sb_check): Use __builtin_clzll when size_t is not the
+ same size as long.
+
+2012-10-29 Alan Modra <amodra@gmail.com>
+
+ * config/tc-ppc.c (ppc_znop): Remove unused vars.
+
+2012-10-26 Alan Modra <amodra@gmail.com>
+
+ PR target/14758
+ * config/tc-ppc.c (ppc_setup_opcodes): Fix comment.
+ (md_assemble): Translate to _DS relocs for ppc32 as well as ppc64.
+ (tc_gen_reloc): Handle _DS relocs in ppc32 mode.
+
+2012-10-22 Simon Baldwin <simonb@google.com>
+
+ * as.c (dump_statistics): Compute data size as the delta between
+ current sbrk(0) and start_sbrk.
+ * (main): Set start_sbrk to sbrk(0) on entry.
+
+2012-10-18 Kai Tietz <ktietz@redhat.com>
+
+ * config/obj-coff.c: Add include of struc-symbol.h header.
+ (coff_frob_symbol): Check that function-aux entries are generated for
+ defined symbols only.
+
+ * doc/as.texinfo: Add missing documentation about section flag
+ exclude.
+
+2012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
+
+ * config/tc-hppa.c (pa_get_number): New.
+ (pa_get_absolute_expression): Simplify.
+ (pa_ip): Use pa_get_number instead of pa_get_absolute_expression
+ to get SOP, SFU and COPR identifiers.
+
+ * config/tc-hppa.c (pa_ip): Reject double floating point stores and
+ loads that reference the right half of a floating point register.
+
+2012-10-13 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
+
+ * config/tc-hppa.c (pa_ip): Limit unit conditions for uxor to those
+ not involving a carry.
+
+2012-10-12 Peter Bergner <bergner@vnet.ibm.com>
+
+ * doc/as.texinfo (-mpwr4, -mpwr7): Fix option name typos.
+
+2012-10-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
+
+ * config/tc-arm.c: Change condition code insertion for
+ lds[hb] instructions from after the 2nd character to after the 3rd.
+ (tCM): Remove macro.
+ (TxCM): Likewise.
+ (TxCM_): Likewise.
+ (TCM): Likewise.
+
+2012-10-09 Nagajyothi Eggone <nagajyothi.eggone@amd.com>
+
+ * config/tc-i386.c (cpu_arch): Add CPU_BDVER3_FLAGS.
+ * doc/c-i386.texi: Add -march=bdver3 option.
+
+2012-10-04 Nick Clifton <nickc@redhat.com>
+
+ * config/tc-v850.c (v850_insert_operand): Use a static buffer for
+ the error message.
+
+2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
+
+ * config/tc-s390.c (s390_parse_cpu): Add new option zEC12.
+ * doc/as.texinfo: Document new option zEC12.
+ * doc/c-s390.texi: Likewise.
+
+2012-10-03 DJ Delorie <dj@redhat.com>
+
+ * config/tc-rl78.c: Change line_separator to '@' so that '|' can
+ be used in expressions.
+
+2012-10-01 Alan Modra <amodra@gmail.com>
+
+ * write.c (chain_frchains_together_1): Reorder assertion to avoid
+ uninit warning.
+
+2012-09-23 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.h (TC_FORCE_RELOCATION): Remove comment.
+ * config/tc-mips.c (calculate_reloc): New function.
+ (append_insn): Use it. Do not resolve compound relocations here.
+ (mips16_macro_build, mips16_ip): Use calculate_reloc.
+ (mips16_immed_extend): New function, split out from...
+ (mips16_immed): ...here.
+ (mips_frob_file): Handle null symbols.
+ (mips_force_relocation): Remove NEWABI handling.
+ (read_reloc_insn, write_reloc_insn): New functions.
+ (md_apply_fix): Report TLS relocations against constants.
+ Use read_reloc_insn, calculate_reloc and write_reloc_insn.
+ Report relocations against constants that can't be resolved
+ at assembly time.
+
+2012-09-23 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * config/tc-mips.c (append_insn) <BFD_RELOC_MIPS_JMP>: Don't
+ mark as incomplete for constant expressions.
+ <BFD_RELOC_MIPS16_JMP>: Likewise.
+
+2012-09-23 Richard Sandiford <rdsandiford@googlemail.com>
+ Maciej W. Rozycki <macro@codesourcery.com>
+
+ * config/tc-mips.h (mips_record_label): Delete.
+ (mips_add_dot_label): Declare.
+ (tc_new_dot_label): Use it.
+ * config/tc-mips.c (mips_assembling_insn): New variable.
+ (md_assemble): Call mips_mark_labels. Set mips_assembling_insn
+ while the main part of the function is executing.
+ (mips_compressed_mark_label): New function, split out from...
+ (mips_compressed_mark_labels): ...here.
+ (append_insn): Don't call mips_mark_labels here.
+ (mips_record_label): Make local.
+ (mips_add_dot_label): New function.
+
+2012-09-23 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.c (SEXT_16BIT): New macro.
+ (mips16_immed): Take the reloc type as a parameter. Do not impose
+ a signed vs. unsigned distinction on the value when a relocation
+ operator was used.
+ (mips16_macro_build, mips16_ip, md_convert_frag): Pass the reloc
+ type to mips16_immed.
+ (macro): Use SEXT_16BIT.
+
+2012-09-23 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.c (read_insn, write_insn, read_compressed_insn):
+ New functions.
+ (install_insn, md_apply_fix, md_convert_frag, mips_handle_align):
+ Use them, and write_compressed_insn.
+
+2012-09-23 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.c (mips_cl_insn): Remove use_extend and extend.
+ (MIPS16_EXTEND): New macro.
+ (mips16_opcode_length): New function.
+ (insn_length): Use it.
+ (create_insn): Update after mips_cl_insn change.
+ (write_compressed_insn): New function.
+ (install_insn): Use it.
+ (append_insn): Use insn_length to check for unextended MIPS16
+ instructions.
+ (mips16_macro_build): Update call to mips16_immed.
+ (mips16_ip): Likewise. Use MIPS16_EXTEND to force an extended
+ instruction.
+ (mips16_immed): Remove use_extend and extend; install EXTEND
+ opcodes in the upper 16 bits of *INSN instead. Keep the
+ instruction extended if it already is. Replace warn, small
+ and ext with a forced_insn_length-like parameter.
+ (md_convert_frag): Update call mips16_immed.
+ Use write_compressed_insn.
+
+2012-09-20 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
+
+ * config/tc-i386.c (cpu_arch): Add .cx16.
+ * doc/c-i386.texi: Document .cx16.
+
+2012-09-19 Steve Ellcey <sellcey@mips.com>
+
+ * configure.tgt: Add mips*-mti-elf* target.
+
+2012-09-18 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
+
+ * config/tc-arm.c: Changed ldra and strl-form mnemonics
+ to lda and stl-form for armv8.
+
+2012-09-17 Yufeng Zhang <yufeng.zhang@arm.com>
+
+ * config/tc-aarch64.c (aarch64_archs): Rename 'armv8' to 'armv8-a'.
+
+2012-09-14 David Edelsohn <dje.gcc@gmail.com>
+
+ * configure: Regenerate.
+
+2012-09-13 Anthony Green <green@moxielogic.com>
+
+ * config/tc-moxie.h (DEFAULT_TARGET_FORMAT): Define.
+ (TARGET_FORMAT): Don't hard-code endian-ness.
+ * config/tc-moxie.c (target_big_endian, moxie_target_format):
+ Define.
+ (md_assemble): Handle bi-endian encodings.
+ (md_shortopts, md_parse_option, md_show_usage, md_apply_fix)
+ (md_number_to_chars, md_chars_to_number): Update for bi-endian
+ support.
+
+2012-09-12 Chris Schlumberger-Socha <chris.schlumberger-socha@arm.com>
+
+ * config/tc-aarch64.c
+ (reloc_table): Add reloc to table entry.
+ (parse_address_main): Add support for #:<reloc_op>:<symbol>.
+ (parse_operands): Check for unused reloc.
+ (md_apply_fix): New case for reloc.
+ (aarch64_force_relocation): Likewise.
+
+2012-09-11 Georg-Johann Lay <avr@gjlay.de>
+
+ PR gas/13503
+ * config/tc-avr.h (TC_VALIDATE_FIX): Skip: BFD_RELOC_AVR_8_LO,
+ BFD_RELOC_AVR_8_HI, BFD_RELOC_AVR_8_HLO.
+
+2012-09-11 Alan Modra <amodra@gmail.com>
+
+ * Makefile.am (bootstrap): Add $EXEEXT to dependency.
+ * Makefile.in: Regenerate.
+
+2012-09-10 Matthias Klose <doko@ubuntu.com>
+
+ * config.in: Disable sanity check for kfreebsd.
+
+2012-09-10 H.J. Lu <hongjiu.lu@intel.com>
+
+ * configure: Regenerated.
+
+2012-09-07 Anthony Green <green@moxielogic.com>
+
+ * config/tc-moxie.c (md_pcrel_from): Branches are now relative
+ to the address following the branch instruction.
+
+2012-09-06 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
+
+ * config/tc-s390.c (set_highgprs_p): New variable.
+ (s390_machinemode): New function.
+ (md_pseudo_table): Add new pseudo command machinemode.
+ (md_parse_option): Set set_highgprs_p to TRUE if -mzarch was
+ specified on command line.
+ (s390_elf_final_processing): Set the highgprs flag in the ELF
+ header depending on set_highgprs_p.
+
+ * doc/c-s390.texi: Document new pseudo machinemode.
+
+2012-09-05 James Lemke <jwlemke@codesourcery.com>
+
+ * doc/c-ppc.texi: Document -mvle.
+ * doc/as.texinfo: Likewise.
+
+2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
+
+ * config/tc-ia64.c (reg_symbol): Add a new register.
+ (indirect_reg): Ditto.
+ (pseudo_func): Add new symbolic constants.
+ (operand_match): Add new operand types recognition.
+ (operand_insn): Add new register recognition.
+ (md_begin): Add new register definition.
+ (specify_resource): Add new register recognition.
+
+2012-09-01 Hans-Peter Nilsson <hp@bitrange.com>
+
+ PR gas/14521
+ * config/tc-mmix.h (tc_frob_file_before_fix): Renumber sections
+ after call to mmix_frob_file.
+
+2012-08-31 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * doc/c-mips.texi (MIPS Opts): Correct a typo in the -mips5
+ option.
+
+2012-08-27 Walter Lee <walt@tilera.com>
+
+ * tc-tilegx.c (O_hw0_plt): Define operator.
+ (O_hw1_plt): Ditto.
+ (O_hw1_last_plt): Ditto.
+ (O_hw2_last_plt): Ditto.
+ (md_begin): Handle new operators.
+ (emit_tilegx_instruction): Ditto.
+ (md_apply_fix): Ditto.
+ * doc/c-tilegx.texi: Document new operators.
+
+2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+
+ * config/tc-arm.c (ARM_ENC_TAB): Add sha1h and sha2op entries.
+ (do_sha1h): New function.
+ (do_sha1su1): Likewise.
+ (do_sha256su0): Likewise.
+ (insns): Add 2 operand SHA instructions.
+
+2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+
+ * config/tc-arm.c (NEON_ENC_TAB): Add sha3op entry.
+ (do_crypto_3op_1): New function.
+ (do_sha1c): Likewise.
+ (do_sha1p): Likewise.
+ (do_sha1m): Likewise.
+ (do_sha1su0): Likewise.
+ (do_sha256h): Likewise.
+ (do_sha256h2): Likewise.
+ (do_sha256su1): Likewise.
+ (insns): Add SHA 3 operand instructions.
+
+2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+
+ * config/tc-arm.c (neon_type_mask): Add P64 type.
+ (type_chk_of_el_type): Handle P64 type.
+ (el_type_of_type_chk): Likewise.
+ (do_neon_vmull): Handle VMULL.P64.
+
+2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+
+ * config/tc-arm.c (NEON_ENC_TAB): Add aes entry.
+ (neon_type_mask): Add N_UNT.
+ (neon_check_type): Don't always decay typed to untyped sizes.
+ (do_crypto_2op_1): New function.
+ (do_aese): Likewise.
+ (do_aesd): Likewise.
+ (do_aesmc.8): Likewise.
+ (do_aesimc.8): Likewise.
+ (insns): Add AES instructions.
+
+2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+
+ * config/tc-arm.c (el_type_type_check): Add handling for 16-bit
+ floating point types.
+ (do_neon_cvttb_2): New function.
+ (do_neon_cvttb_1): Likewise.
+ (do_neon_cvtb): Refactor to use do_neon_cvttb_1.
+ (do_neon_cvtt): Likewise.
+
+2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+
+ * config/tc-arm.c (NEON_ENC_TAB): Add vrint entries.
+ (neon_cvt_mode): Add neon_cvt_mode_r.
+ (do_vrint_1): New function.
+ (do_vrint_x): Likewise.
+ (do_vrint_z): Likewise.
+ (do_vrint_r): Likewise.
+ (do_vrint_a): Likewise.
+ (do_vrint_n): Likewise.
+ (do_vrint_p): Likewise.
+ (do_vrint_m): Likewise.
+ (insns): Add VRINT instructions.
+
+2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+
+ * config/tc-arm.c (NEON_ENC_TAB): Add vcvta entry.
+ (neon_cvt_mode): New enumeration.
+ (do_vfp_nsyn_cvt_fpv8): New function.
+ (do_neon_cvt_1): Add support for new conversions.
+ (do_neon_cvtr): Use neon_cvt_mode enumerator.
+ (do_neon_cvt): Likewise.
+ (do_neon_cvta): New function.
+ (do_neon_cvtn): Likewise.
+ (do_neon_cvtp): Likewise.
+ (do_neon_cvtm): Likewise.
+ (insns): Add new VCVT instructions.
+
+2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm>
+
+ * config/tc-arm.c (CVT_FLAVOUR_VAR): New define.
+ (CVT_VAR): New helper define.
+ (neon_cvt_flavour): New enumeration, function renamed...
+ (get_neon_cvt_flavour): ...to this.
+ (do_vfp_nsyn_cvt): Update to use new neon_cvt_flavour.
+ (do_vfp_nsyn_cvtz): Likewise.
+ (do_neon_cvt_1): Likewise.
+
+2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+
+ * config/tc-arm.c (NEON_ENC_TAB): Add vmaxnm, vminnm entries.
+ (vfp_or_neon_is_neon_bits): Add NEON_CHECK_ARCH8 enumerator.
+ (vfp_or_neon_is_neon): Add check for SIMD for ARMv8.
+ (do_maxnm): New function.
+ (insns): Add vmaxnm, vminnm entries.
+
+2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+
+ * config/tc-arm.c (NEON_ENC_TAB): Add entries for VSEL.
+ (NEON_ENC_FPV8_): New define.
+ (do_vfp_nsyn_fpv8): New function.
+ (do_vsel): Likewise.
+ (insns): Add VSEL instructions.
+
+2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+
+ * config/tc-arm.c (do_rm_rn): New function.
+ (do_strlex): Likewise.
+ (do_t_strlex): Likewise.
+ (insns): Add support for LDRA/STRL instructions.
+
+2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+
+ * config/tc-arm.c (do_t_bkpt_hlt1): New function.
+ (do_t_hlt): New function.
+ (do_t_bkpt): Use do_t_bkpt_hlt1.
+ (insns): Add HLT.
+
+2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+
+ * config/tc-arm.c (insns): Add DCPS instruction.
+
+2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+
+ * config/tc-arm.c (T16_32_TAB): Add _sevl.
+ (insns): Add SEVL.
+
+2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+
+ * config/tc-arm.c (asm_barrier_opt): Add arch field.
+ (mark_feature_used): New function.
+ (parse_barrier): Check specified option is valid for the
+ specified architecture.
+ (UL_BARRIER): New macro.
+ (barrier_opt_names): Update for new barrier options.
+
+2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+
+ * config/tc-arm.c (do_setend): Warn on deprecated SETEND.
+ (do_t_setend): Likewise.
+
+2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+
+ * config/tc-arm.c (do_t_it): Fully initialise now_it.
+ (new_automatic_it_block): Likewise.
+ (handle_it_block): Record whether current instruction is
+ conditionally executed.
+ * config/tc-arm.c (depr_insn_mask): New structure.
+ (depr_it_insns): New variable.
+ (it_fsm_post_encode): Warn on deprecated uses.
+ * config/tc-arm.h (current_it): Add new fields.
+
+2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+
+ * config/tc-arm.c (deprecated_coproc_regs_s): New structure.
+ (deprecated_coproc_regs): New variable.
+ (deprecated_coproc_reg_count): Likewise.
+ (do_co_reg): Error on obsolete & warn on deprecated registers.
+
+2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+
+ * config/tc-arm.c (check_obsolete): New function.
+ (do_rd_rm_rn): Check swp{b} for obsoletion.
+
+2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+
+ * config/tc-arm.h (arm_ext_v8): New variable.
+ (fpu_vfp_ext_armv8): Likewise.
+ (fpu_neon_ext_armv8): Likewise.
+ (fpu_crypto_ext_armv8): Likewise.
+ (arm_archs): Add armv8-a.
+ (arm_extensions): Add crypto, fp, and simd.
+ (arm_fpus): Add fp-armv8, neon-fp-armv8, crypto-neon-fp-armv8.
+ (cpu_arch_ver): Add support for ARMv8.
+ (aeabi_set_public_sttributes): Likewise.
+ * doc/c-arm.texi (ARM Options): Document new architecture and
+ extension options for ARMv8.
+
2012-08-20 H.J. Lu <hongjiu.lu@intel.com>
* doc/as.texinfo: Replace --n32 with --x32.
CPU_BTVER2_FLAGS.
(i386_align_code): Add case for PROCESSOR_BT.
- * config/tc-i386.h (enum processor_type): Add PROCESSOR_BT.
+ * config/tc-i386.h (enum processor_type): Add PROCESSOR_BT.
* doc/c-i386.texi: Add -march={btver1, btver2} options.
For older changes see ChangeLog-2011
\f
+Copyright (C) 2012 Free Software Foundation, Inc.
+
+Copying and distribution of this file, with or without modification,
+are permitted in any medium without royalty provided the copyright
+notice and this notice are preserved.
+
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