Updated Spanish translation for the bfd/ sub-directory, and updated Ukranian translat...

[deliverable/binutils-gdb.git] / gas / ChangeLog

diff --git a/gas/ChangeLog b/gas/ChangeLog
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+2018-03-19  Nick Clifton  <nickc@redhat.com>
+
+       * po/uk.po: Updated Ukranian translation.
+
+2018-03-16  Jim Wilson  <jimw@sifive.com>
+
+       * config/tc-riscv.c (check_absolute_expr): Expand comment.  New
+       parameter maybe_csr.  If maybe_csr and O_symbol, print CSR name.
+       (riscv_ip): Add new argument to check_absolute_expr calls.
+       * testsuite/gas/riscv/bad-csr.d: New.
+       * testsuite/gas/riscv/bad-csr.l: New.
+       * testsuite/gas/riscv/bad-csr.s: New.
+
+2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
+
+       * config/tc-riscv.c (opcode_name_list): New.
+       (opcode_names_hash): Likewise.
+       (init_opcode_names_hash): Likewise.
+       (opcode_name_lookup): Likewise.
+       (validate_riscv_insn): New argument length, and add new format
+       which used in .insn directive.
+       (md_begin): Refine hash table initialization logic into
+       init_opcode_hash.
+       (init_opcode_hash): New.
+       (my_getOpcodeExpression): Parse opcode name for .insn.
+       (riscv_ip): New argument hash, able to handle .insn directive.
+       (s_riscv_insn): Handler for .insn directive.
+       (riscv_pseudo_table): New entry for .insn.
+       * doc/c-riscv.texi: Add documentation for .insn directive.
+       * testsuite/gas/riscv/insn.d: Add testcase for .insn directive.
+       * testsuite/gas/riscv/insn.s: Likewise.
+
+2018-03-13  Nick Clifton  <nickc@redhat.com>
+
+       * po/ru.po: Updated Russian translation.
+
+2018-03-09  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * config/tc-i386.c (optimize_encoding): Encode EVEX instructions
+       with VEX128 if EVEX encoding isn't required.
+       * testsuite/gas/i386/optimize-1.d: Updated.
+       * testsuite/gas/i386/x86-64-optimize-2.d: Likewise.
+
+2018-03-09  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * config/tc-i386.c (check_VecOperations): Strip whitespace.
+       * testsuite/gas/i386/optimize-1.s: Add whitespaces before
+       {%k7} and {z},
+       * testsuite/gas/i386/x86-64-optimize-2.s: Likewise.
+
+2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * config/tc-i386.c (set_cpu_arch): Set cpu_arch_isa_flags.
+       (md_parse_option): Likewise.
+       (optimize_encoding): Check i.tm.cpu_flags and cpu_arch_isa_flags
+       for cpuavx512vl instead of cpu_arch_flags.  Optimize EVEX with
+       EVEX128 when EVEX encoding is required.
+       * testsuite/gas/i386/i386.exp: Run optimize-4, optimize-5,
+       x86-64-optimize-5 and x86-64-optimize-6.
+       * testsuite/gas/i386/optimize-1.d: Updated.
+       * testsuite/gas/i386/x86-64-optimize-2.d: Likewise.
+       * testsuite/gas/i386/optimize-4.d: New file.
+       * testsuite/gas/i386/optimize-4.s: Likewise.
+       * testsuite/gas/i386/optimize-5.d: Likewise.
+       * testsuite/gas/i386/optimize-5.s: Likewise.
+       * testsuite/gas/i386/x86-64-optimize-5.d: Likewise.
+       * testsuite/gas/i386/x86-64-optimize-5.s: Likewise.
+       * testsuite/gas/i386/x86-64-optimize-6.d: Likewise.
+       * testsuite/gas/i386/x86-64-optimize-6.s: Likewise.
+
+2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * config/tc-i386.c (optimize_encoding): Also encode "clr reg64"
+       as "xor reg32, reg32".
+       * testsuite/gas/i386/x86-64-optimize-1.s: Add "clr reg64" tests.
+       * testsuite/gas/i386/x86-64-optimize-1.d: Updated.
+
+2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * NEWS: Mention -mold-gcc removal.
+       * config/tc-i386.c (i386_error): Remove old_gcc_only.
+       (old_gcc): Removed.
+       (match_template): Remove old gcc support.
+       (OPTION_MOLD_GCC): Removed.
+       (OPTION_MRELAX_RELOCATIONS): Updated.
+       (md_longopts): Remove OPTION_MOLD_GCC.
+       (md_parse_option): Likewise.
+       (md_show_usage): Remove -mold-gcc.
+       * testsuite/gas/i386/general.s: Convert fsub/fdiv tests for old
+       (<= 2.8.1) versions of gcc.
+       * testsuite/gas/i386/intel.s: Likewise.
+       * testsuite/gas/i386/general.l: Updated.
+       * testsuite/gas/i386/intel-intel.d: Likewise.
+       * testsuite/gas/i386/intel.d: Likewise.
+       * testsuite/gas/i386/intel.e: Likewise.
+       * testsuite/gas/i386/i386.exp: Don't pass -mold-gcc to general.
+
+2018-03-08  Jan Beulich  <jbeulich@suse.com>
+
+       * config/tc-i386.c (is_evex_encoding): New.
+       (optimize_encoding, md_assemble, md_assemble,
+       VEX_check_operands, build_modrm_byte): Use is_evex_encoding.
+       (build_evex_prefix): Derive EVEX length field from actual
+       operands if the template allows multiple ones.
+
+2018-03-08  Jan Beulich  <jbeulich@suse.com>
+
+       * config/tc-i386.c (build_modrm_byte): Make VexNDD handling cope
+       with 3rd (immediate) operand.
+
 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 
        * config/tc-i386.c (XMMWORD_MNEM_SUFFIX, YMMWORD_MNEM_SUFFIX,