[PowerPC VLE] Add SPE2 and EFS2 instructions support

[deliverable/binutils-gdb.git] / gas / NEWS

diff --git a/gas/NEWS b/gas/NEWS
index feec9a6265b9b7b7293afd0f06a59e88228b35bc..843f6c1120e0df2aa25bd018ba1e0d4bb73a75ac 100644 (file)
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,5 +1,68 @@
 -*- text -*-
 
+* Add support for loaction views in DWARF debug line information.
+
+Changes in 2.29:
+
+* Add support for ELF SHF_GNU_MBIND.
+
+* Add support for the WebAssembly file format and wasm32 ELF conversion.
+
+* PowerPC gas now checks that the correct register class is used in
+  instructions.  For instance, "addi %f4,%cr3,%r31" warns three times
+  that the registers are invalid.
+
+* Add support for the Texas Instruments PRU processor.
+
+* Support for the ARMv8-R architecture and Cortex-R52 processor has been
+  added to the ARM port.
+
+Changes in 2.28:
+
+* Add support for the RISC-V architecture.
+
+* Add support for the ARM Cortex-M23 and Cortex-M33 processors.
+
+Changes in 2.27:
+
+* Default to --enable-compressed-debug-sections=gas for Linux/x86 targets.
+
+* Add --no-pad-sections to stop the assembler from padding the end of output
+  sections up to their alignment boundary.
+
+* Support for the ARMv8-M architecture has been added to the ARM port.  Support
+  for the ARMv8-M Security and DSP Extensions has also been added to the ARM
+  port.
+
+* ARC backend accepts .extInstruction, .extCondCode, .extAuxRegister, and
+  .extCoreRegister pseudo-ops that allow an user to define custom
+  instructions, conditional codes, auxiliary and core registers.
+
+* Add a configure option --enable-elf-stt-common to decide whether ELF
+  assembler should generate common symbols with the STT_COMMON type by
+  default.  Default to no.
+
+* New command line option --elf-stt-common= for ELF targets to control
+  whether to generate common symbols with the STT_COMMON type.
+
+* Add ability to set section flags and types via numeric values for ELF
+  based targets.
+
+* Add a configure option --enable-x86-relax-relocations to decide whether
+  x86 assembler should generate relax relocations by default.  Default to
+  yes, except for x86 Solaris targets older than Solaris 12.
+
+* New command line option -mrelax-relocations= for x86 target to control
+  whether to generate relax relocations.
+
+* New command line option -mfence-as-lock-add=yes for x86 target to encode
+  lfence, mfence and sfence as "lock addl $0x0, (%[re]sp)".
+
+* Add assembly-time relaxation option for ARC cpus.
+
+* Add --with-cpu=TYPE configure option for ARC gas.  This allows the default
+  cpu type to be adjusted at configure time.
+
 Changes in 2.26:
 
 * Add a configure option --enable-compressed-debug-sections={all,gas} to
@@ -655,7 +718,7 @@ Changes in 1.93.01:
   of new CPUs and formats, lots of bugs fixed.
 
 \f
-Copyright (C) 2012-2016 Free Software Foundation, Inc.
+Copyright (C) 2012-2017 Free Software Foundation, Inc.
 
 Copying and distribution of this file, with or without modification,
 are permitted in any medium without royalty provided the copyright