Replace a couple of assertions in the BFD library that can be triggered by attempts...

[deliverable/binutils-gdb.git] / gas / NEWS

diff --git a/gas/NEWS b/gas/NEWS
index 3903c383c191428f0e39cf4a036d8d6243e2552f..9bbeaeb8c59a43267f7e9a22fa04e54116ca7cdb 100644 (file)
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,9 +1,59 @@
 -*- text -*-
 
-* For MIPS, Add -m[no-]fix-loongson3-llsc option to fix (or not) Loongson3 LLSC
-  Errata.  Add a --enable-mips-fix-loongson3-llsc=[yes|no] configure time option
-  to set the default behavior. Set the default if the configure option is not used
-  to "no".
+* Add -mlfence-after-load=, -mlfence-before-indirect-branch= and
+  -mlfence-before-ret= options to x86 assembler to help mitigate
+  CVE-2020-0551.
+
+* Add --gdwarf-5 option to the assembler to generate DWARF 5 debug output
+  (if such output is being generated).  Added the ability to generate
+  version 5 .debug_line sections.
+
+Changes in 2.34:
+
+* Add -malign-branch-boundary=NUM, -malign-branch=TYPE[+TYPE...],
+  -malign-branch-prefix-size=NUM and -mbranches-within-32B-boundaries
+  options to x86 assembler to align branches within a fixed boundary
+  with segment prefixes or NOPs.
+
+* Add support for Zilog eZ80 and Zilog Z180 CPUs.
+
+* Add support for z80-elf target.
+
+* Add support for relocation of each byte or word of multibyte value to Z80
+  targets (just use right shift to 0, 8, 16, or 24 bits or AND operation
+  with 0xff/0xffff mask): ld a, label >> 16 \ ld hl, label & 0xffff
+
+* Add SDCC support for Z80 targets.
+
+Changes in 2.33:
+
+* Add support for the Arm Scalable Vector Extension version 2 (SVE2)
+  instructions.
+
+* Add support for the Arm Transactional Memory Extension (TME)
+  instructions.
+
+* Add support for the Armv8.1-M Mainline and M-profile Vector Extension (MVE)
+  instructions.
+
+* For MIPS, Add -m[no-]fix-loongson3-llsc option to fix (or not) Loongson3
+  LLSC Errata.  Add a --enable-mips-fix-loongson3-llsc=[yes|no] configure
+  time option to set the default behavior. Set the default if the configure
+  option is not used to "no".
+
+* Add support for the Arm Cortex-A76AE, Cortex-A77 and Cortex-M35P
+  processors.
+
+* Add support for the AArch64 Cortex-A34, Cortex-A65, Cortex-A65AE,
+  Cortex-A76AE, and Cortex-A77 processors.
+
+* Add .float16 directive for both Arm and AArch64 to allow encoding of 16-bit
+  floating point literals.  Add .float16_format directive and
+  -mfp16-format=[ieee|alternative] option for Arm to control the format of the
+  encoding.
+
+* Add --gdwarf-cie-version command line flag.  This allows control over which
+  version of DWARF CIE the assembler creates.
 
 Changes in 2.32:
 
@@ -772,7 +822,7 @@ Changes in 1.93.01:
   of new CPUs and formats, lots of bugs fixed.
 
 \f
-Copyright (C) 2012-2019 Free Software Foundation, Inc.
+Copyright (C) 2012-2020 Free Software Foundation, Inc.
 
 Copying and distribution of this file, with or without modification,
 are permitted in any medium without royalty provided the copyright