aarch64: Add DSB instruction Armv8.7-a variant

[deliverable/binutils-gdb.git] / gas / NEWS

diff --git a/gas/NEWS b/gas/NEWS
index c1fffc618aead3bf8ec5fde0267045c6a26c9e49..b993464a67c962131723999614470926197b8969 100644 (file)
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,5 +1,30 @@
 -*- text -*-
 
+* Add support for Intel AVX VNNI instructions.
+
+* Add support for Intel HRESET instruction.
+
+* Add support for Intel UINTR instructions.
+
+* Support non-absolute segment values for i386 lcall and ljmp.
+
+* When setting the link order attribute of ELF sections, it is now possible to
+  use a numeric section index instead of symbol name.
+
+* Add support for Cortex-A78, Cortex-A78AE and Cortex-X1 for AArch64 and ARM.
+  Add support for Cortex-R82, Neoverse V1, and Neoverse N2 for ARM.
+
+* Add support for ETMv4 (Embedded Trace Macrocell), ETE (Embedded Trace
+  Extension), TRBE (Trace Buffer Extension), CSRE (Call Stack Recorder
+  Extension) and BRBE (Branch Record Buffer Extension) system registers for
+  AArch64.
+
+* Add support for Armv8-R and Armv8.7-A AArch64.
+
+* Add support for DSB memory nXS barrier instruction for Armv8.7 AArch64.
+
+* Add support for Intel TDX instructions.
+
 * Add support for Intel Key Locker instructions.
 
 * Added a .nop directive to generate a single no-op instruction in a target