}
static int
-in_range_p (Expr_Node *expr, int from, int to, unsigned int mask)
+in_range_p (Expr_Node *exp, int from, int to, unsigned int mask)
{
- int val = EXPR_VALUE (expr);
- if (expr->type != Expr_Node_Constant)
+ int val = EXPR_VALUE (exp);
+ if (exp->type != Expr_Node_Constant)
return 0;
if (val < from || val > to)
return 0;
/* Anomaly 05000074 */
if (ENABLE_AC_05000074
+ && dsp32 != NULL && dsp16_grp1 != NULL
&& (dsp32->value & 0xf780) == 0xc680
&& ((dsp16_grp1->value & 0xfe40) == 0x9240
|| (dsp16_grp1->value & 0xfe08) == 0xba08
%type <reg> a_minusassign
%type <macfunc> multiply_halfregs
%type <macfunc> assign_macfunc
-%type <macfunc> a_macfunc
+%type <macfunc> a_macfunc
%type <expr> expr_1
%type <instr> asm_1
%type <r0> vmod
| REG ASSIGN REG
{
- if (IS_ALLREG ($1) && IS_ALLREG ($3))
+ if ((IS_GENREG ($1) && IS_GENREG ($3))
+ || (IS_GENREG ($1) && IS_DAGREG ($3))
+ || (IS_DAGREG ($1) && IS_GENREG ($3))
+ || (IS_DAGREG ($1) && IS_DAGREG ($3))
+ || (IS_GENREG ($1) && $3.regno == REG_USP)
+ || ($1.regno == REG_USP && IS_GENREG ($3))
+ || (IS_DREG ($1) && IS_SYSREG ($3))
+ || (IS_PREG ($1) && IS_SYSREG ($3))
+ || (IS_SYSREG ($1) && IS_DREG ($3))
+ || (IS_SYSREG ($1) && IS_PREG ($3))
+ || (IS_SYSREG ($1) && $3.regno == REG_USP))
{
- notethat ("REGMV: allregs = allregs\n");
$$ = bfin_gen_regmv (&$3, &$1);
}
else
$$ = bfin_gen_pseudodbg (3, 5, 0);
}
+ | HLT
+ {
+ notethat ("psedoDEBUG: HLT\n");
+ $$ = bfin_gen_pseudodbg (3, 4, 0);
+ }
+
| DBGA LPAREN HALF_REG COMMA expr RPAREN
{
- notethat ("pseudodbg_assert: DBGA (dregs_lo , uimm16 )\n");
+ notethat ("pseudodbg_assert: DBGA (regs_lo/hi , uimm16 )\n");
$$ = bfin_gen_pseudodbg_assert (IS_H ($3), &$3, uimm16 ($5));
}
-
+
| DBGAH LPAREN REG COMMA expr RPAREN
{
- notethat ("pseudodbg_assert: DBGAH (dregs , uimm16 )\n");
+ notethat ("pseudodbg_assert: DBGAH (regs , uimm16 )\n");
$$ = bfin_gen_pseudodbg_assert (3, &$3, uimm16 ($5));
}
| DBGAL LPAREN REG COMMA expr RPAREN
{
- notethat ("psedodbg_assert: DBGAL (dregs , uimm16 )\n");
+ notethat ("psedodbg_assert: DBGAL (regs , uimm16 )\n");
$$ = bfin_gen_pseudodbg_assert (2, &$3, uimm16 ($5));
}
ccstat:
CCREG cc_op STATUS_REG
{
- $$.r0 = $3.regno;
- $$.x0 = $2.r0;
- $$.s0 = 0;
+ $$.r0 = $3.regno;
+ $$.x0 = $2.r0;
+ $$.s0 = 0;
}
| CCREG cc_op V
{
- $$.r0 = 0x18;
- $$.x0 = $2.r0;
- $$.s0 = 0;
+ $$.r0 = 0x18;
+ $$.x0 = $2.r0;
+ $$.s0 = 0;
}
| STATUS_REG cc_op CCREG
{
- $$.r0 = $1.regno;
- $$.x0 = $2.r0;
- $$.s0 = 1;
+ $$.r0 = $1.regno;
+ $$.x0 = $2.r0;
+ $$.s0 = 1;
}
| V cc_op CCREG
{
- $$.r0 = 0x18;
- $$.x0 = $2.r0;
- $$.s0 = 1;
+ $$.r0 = 0x18;
+ $$.x0 = $2.r0;
+ $$.s0 = 1;
}
;
}
static int
-value_match (Expr_Node *expr, int sz, int sign, int mul, int issigned)
+value_match (Expr_Node *exp, int sz, int sign, int mul, int issigned)
{
int umax = (1 << sz) - 1;
int min = -1 << (sz - 1);
int max = (1 << (sz - 1)) - 1;
- int v = (EXPR_VALUE (expr)) & 0xffffffff;
+ int v = (EXPR_VALUE (exp)) & 0xffffffff;
if ((v % mul) != 0)
{