/* tc-aarch64.c -- Assemble for the AArch64 ISA
- Copyright (C) 2009-2016 Free Software Foundation, Inc.
+ Copyright (C) 2009-2017 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
/* Which ABI to use. */
enum aarch64_abi_type
{
- AARCH64_ABI_LP64 = 0,
- AARCH64_ABI_ILP32 = 1
+ AARCH64_ABI_NONE = 0,
+ AARCH64_ABI_LP64 = 1,
+ AARCH64_ABI_ILP32 = 2
};
+#ifndef DEFAULT_ARCH
+#define DEFAULT_ARCH "aarch64"
+#endif
+
+/* DEFAULT_ARCH is initialized in gas/configure.tgt. */
+static const char *default_arch = DEFAULT_ARCH;
+
/* AArch64 ABI for the output file. */
-static enum aarch64_abi_type aarch64_abi = AARCH64_ABI_LP64;
+static enum aarch64_abi_type aarch64_abi = AARCH64_ABI_NONE;
/* When non-zero, program to a 32-bit model, in which the C data types
int, long and all pointer types are 32-bit objects (ILP32); or to a
static bfd_boolean parse_operands (char *, const aarch64_opcode *);
static bfd_boolean programmer_friendly_fixup (aarch64_instruction *);
-/* Diagnostics inline function utilites.
+/* Diagnostics inline function utilities.
- These are lightweight utlities which should only be called by parse_operands
+ These are lightweight utilities which should only be called by parse_operands
and other parsers. GAS processes each assembly line by parsing it against
instruction template(s), in the case of multiple templates (for the same
mnemonic name), those templates are tried one by one until one succeeds or
the parsing; we don't want to slow down the whole parsing by recording
non-user errors in detail.
- Remember that the objective is to help GAS pick up the most approapriate
+ Remember that the objective is to help GAS pick up the most appropriate
error message in the case of multiple templates, e.g. FMOV which has 8
templates. */
BASIC_REG_TYPE(FP_S) /* s[0-31] */ \
BASIC_REG_TYPE(FP_D) /* d[0-31] */ \
BASIC_REG_TYPE(FP_Q) /* q[0-31] */ \
- BASIC_REG_TYPE(CN) /* c[0-7] */ \
BASIC_REG_TYPE(VN) /* v[0-31] */ \
BASIC_REG_TYPE(ZN) /* z[0-31] */ \
BASIC_REG_TYPE(PN) /* p[0-15] */ \
msg = N_("128-bit SIMD scalar or floating-point quad precision "
"register expected");
break;
- case REG_TYPE_CN:
- msg = N_("C0 - C15 expected");
- break;
case REG_TYPE_R_Z_BHSDQ_V:
case REG_TYPE_R_Z_BHSDQ_VZP:
msg = N_("register expected");
set_syntax_error (error);
}
-/* Similiar to first_error, but this function accepts formatted error
+/* Similar to first_error, but this function accepts formatted error
message. */
static void
first_error_fmt (const char *format, ...)
succeeds; otherwise return FALSE.
Accept only one occurrence of:
- 8b 16b 2h 4h 8h 2s 4s 1d 2d
+ 4b 8b 16b 2h 4h 8h 2s 4s 1d 2d
b h s d q */
static bfd_boolean
parse_vector_type_for_operand (aarch64_reg_type reg_type,
element_size = 64;
break;
case 'q':
- if (width == 1)
+ if (reg_type == REG_TYPE_ZN || width == 1)
{
type = NT_q;
element_size = 128;
first_error (_("missing element size"));
return FALSE;
}
- if (width != 0 && width * element_size != 64 && width * element_size != 128
- && !(width == 2 && element_size == 16))
+ if (width != 0 && width * element_size != 64
+ && width * element_size != 128
+ && !(width == 2 && element_size == 16)
+ && !(width == 4 && element_size == 8))
{
first_error_fmt (_
("invalid element size %d and vector size combination %c"),
/* Expect index. In the new scheme we cannot have
Vn.[bhsdq] represent a scalar. Therefore any
Vn.[bhsdq] should have an index following it.
- Except in reglists ofcourse. */
+ Except in reglists of course. */
atype.defined |= NTA_HASINDEX;
else
atype.defined |= NTA_HASTYPE;
return PARSE_FAIL;
}
- if (in_reg_list == TRUE)
+ if (in_reg_list)
{
first_error (_("index not allowed inside register list"));
return PARSE_FAIL;
}
/* Can't use symbol_new here, so have to create a symbol and then at
- a later date assign it a value. Thats what these functions do. */
+ a later date assign it a value. That's what these functions do. */
static void
symbol_locate (symbolS * symbolP,
return inst.reloc.type == BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP;
}
-/* Assign the immediate value to the relavant field in *OPERAND if
+/* Assign the immediate value to the relevant field in *OPERAND if
RELOC->EXP is a constant expression; otherwise, flag that *OPERAND
needs an internal fixup in a later stage.
ADDR_OFF_P determines whether it is the field ADDR.OFFSET.IMM or
0, /* adr_type */
0,
0,
- BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC,
+ BFD_RELOC_AARCH64_TLSDESC_ADD_LO12,
BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC,
0},
/* Get to the page containing GOT TLS entry for a symbol.
The same as GD, we allocate two consecutive GOT slots
for module index and module offset, the only difference
- with GD is the module offset should be intialized to
+ with GD is the module offset should be initialized to
zero without any outstanding runtime relocation. */
{"tlsldm", 0,
BFD_RELOC_AARCH64_TLSLD_ADR_PREL21, /* adr_type */
switch (mode)
{
case SHIFTED_LOGIC_IMM:
- if (aarch64_extend_operator_p (kind) == TRUE)
+ if (aarch64_extend_operator_p (kind))
{
set_syntax_error (_("extending shift is not permitted"));
return FALSE;
operand->shifter.amount = 1;
else if (exp.X_op == O_absent)
{
- if (aarch64_extend_operator_p (kind) == FALSE || exp_has_prefix)
+ if (!aarch64_extend_operator_p (kind) || exp_has_prefix)
{
set_syntax_error (_("missing shift amount"));
return FALSE;
instruction->reloc.type = BFD_RELOC_UNUSED;
}
-/* Data strutures storing one user error in the assembly code related to
+/* Data structures storing one user error in the assembly code related to
operands. */
struct operand_error_record
const aarch64_opnd_qualifier_t *qualifiers = *qualifiers_list;
/* Most opcodes has much fewer patterns in the list. */
- if (empty_qualifier_sequence_p (qualifiers) == TRUE)
+ if (empty_qualifier_sequence_p (qualifiers))
{
DEBUG_TRACE_IF (i == 0, "empty list of qualifier sequence");
break;
return idx;
}
-/* Assign qualifiers in the qualifier seqence (headed by QUALIFIERS) to the
+/* Assign qualifiers in the qualifier sequence (headed by QUALIFIERS) to the
corresponding operands in *INSTR. */
static inline void
/* Delimiter. */
if (str[0] != '\0')
- strcat (buf, i == 0 ? " " : ",");
+ strcat (buf, i == 0 ? " " : ", ");
/* Append the operand string. */
strcat (buf, str);
else
{
gas_assert (idx >= 0);
- as_bad (_("operand %d should be %s -- `%s'"), idx + 1,
+ as_bad (_("operand %d must be %s -- `%s'"), idx + 1,
aarch64_get_operand_desc (opd_code), str);
}
break;
{
/* Most opcodes has much fewer patterns in the list.
First NIL qualifier indicates the end in the list. */
- if (empty_qualifier_sequence_p (*qualifiers_list) == TRUE)
+ if (empty_qualifier_sequence_p (*qualifiers_list))
break;
if (i != qlf_idx)
detail->error ? detail->error : _("immediate value"),
detail->data[0], detail->data[1], idx + 1, str);
else
- as_bad (_("%s expected to be %d at operand %d -- `%s'"),
+ as_bad (_("%s must be %d at operand %d -- `%s'"),
detail->error ? detail->error : _("immediate value"),
detail->data[0], idx + 1, str);
break;
break;
case AARCH64_OPDE_UNALIGNED:
- as_bad (_("immediate value should be a multiple of "
+ as_bad (_("immediate value must be a multiple of "
"%d at operand %d -- `%s'"),
detail->data[0], idx + 1, str);
break;
When this function is called, the operand error information had
been collected for an assembly line and there will be multiple
- errors in the case of mulitple instruction templates; output the
+ errors in the case of multiple instruction templates; output the
error message that most closely describes the problem. */
static void
}
/* Find the error kind of the highest severity. */
- DEBUG_TRACE ("multiple opcode entres with error kind");
+ DEBUG_TRACE ("multiple opcode entries with error kind");
kind = AARCH64_OPDE_NIL;
for (curr = head; curr != NULL; curr = curr->next)
{
case AARCH64_OPND_Rt_SYS:
case AARCH64_OPND_Rd_SP:
case AARCH64_OPND_Rn_SP:
+ case AARCH64_OPND_Rm_SP:
case AARCH64_OPND_Fd:
case AARCH64_OPND_Fn:
case AARCH64_OPND_Fm:
return TRUE;
}
-/* A primitive log caculator. */
+/* A primitive log calculator. */
static inline unsigned int
get_logsz (unsigned int size)
gas_assert (logsz <= 4);
/* In reloc.c, these pseudo relocation types should be defined in similar
- order as above reloc_ldst_lo12 array. Because the array index calcuation
+ order as above reloc_ldst_lo12 array. Because the array index calculation
below relies on this. */
return reloc_ldst_lo12[inst.reloc.type - BFD_RELOC_AARCH64_LDST_LO12][logsz];
}
backtrack_pos = str;
}
- /* Expect comma between operands; the backtrack mechanizm will take
+ /* Expect comma between operands; the backtrack mechanism will take
care of cases of omitted optional operand. */
if (i > 0 && ! skip_past_char (&str, ','))
{
case AARCH64_OPND_Rd_SP:
case AARCH64_OPND_Rn_SP:
case AARCH64_OPND_SVE_Rn_SP:
+ case AARCH64_OPND_Rm_SP:
po_int_reg_or_fail (REG_TYPE_R_SP);
break;
info->qualifier = AARCH64_OPND_QLF_S_D;
break;
+ case AARCH64_OPND_SVE_Zm3_INDEX:
+ case AARCH64_OPND_SVE_Zm3_22_INDEX:
+ case AARCH64_OPND_SVE_Zm4_INDEX:
case AARCH64_OPND_SVE_Zn_INDEX:
reg_type = REG_TYPE_ZN;
goto vector_reg_index;
goto failure;
break;
- case AARCH64_OPND_Cn:
- case AARCH64_OPND_Cm:
- po_reg_or_fail (REG_TYPE_CN);
- if (val > 15)
+ case AARCH64_OPND_CRn:
+ case AARCH64_OPND_CRm:
{
- set_fatal_syntax_error (_(get_reg_expected_msg (REG_TYPE_CN)));
- goto failure;
+ char prefix = *(str++);
+ if (prefix != 'c' && prefix != 'C')
+ goto failure;
+
+ po_imm_nc_or_fail ();
+ if (val > 15)
+ {
+ set_fatal_syntax_error (_(N_ ("C0 - C15 expected")));
+ goto failure;
+ }
+ info->qualifier = AARCH64_OPND_QLF_CR;
+ info->imm.value = val;
+ break;
}
- inst.base.operands[i].reg.regno = val;
- break;
case AARCH64_OPND_SHLL_IMM:
case AARCH64_OPND_IMM_VLSR:
case AARCH64_OPND_SVE_UIMM7:
case AARCH64_OPND_SVE_UIMM8:
case AARCH64_OPND_SVE_UIMM8_53:
+ case AARCH64_OPND_IMM_ROT1:
+ case AARCH64_OPND_IMM_ROT2:
+ case AARCH64_OPND_IMM_ROT3:
+ case AARCH64_OPND_SVE_IMM_ROT1:
+ case AARCH64_OPND_SVE_IMM_ROT2:
po_imm_nc_or_fail ();
info->imm.value = val;
break;
/* skip_p */ 0);
break;
+ case AARCH64_OPND_ADDR_SIMM10:
+ po_misc_or_fail (parse_address (&str, info));
+ if (info->addr.pcrel || info->addr.offset.is_reg
+ || !info->addr.preind || info->addr.postind)
+ {
+ set_syntax_error (_("invalid addressing mode"));
+ goto failure;
+ }
+ if (inst.reloc.type != BFD_RELOC_UNUSED)
+ {
+ set_syntax_error (_("relocation not allowed"));
+ goto failure;
+ }
+ assign_imm_if_const_or_fixup_later (&inst.reloc, info,
+ /* addr_off_p */ 1,
+ /* need_libopcodes_p */ 1,
+ /* skip_p */ 0);
+ break;
+
case AARCH64_OPND_ADDR_UIMM12:
po_misc_or_fail (parse_address (&str, info));
if (info->addr.pcrel || info->addr.offset.is_reg
else
{
set_fatal_syntax_error
- (_("writeback value should be an immediate constant"));
+ (_("writeback value must be an immediate constant"));
goto failure;
}
}
/* No qualifier. */
break;
+ case AARCH64_OPND_SVE_ADDR_RI_S4x16:
case AARCH64_OPND_SVE_ADDR_RI_S4xVL:
case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL:
case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL:
{
case ldst_pos:
case ldst_imm9:
+ case ldst_imm10:
case ldst_unscaled:
case ldst_unpriv:
/* Loading/storing the base register is unpredictable if writeback. */
REGDEF (wzr, 31, Z_32), REGDEF (WZR, 31, Z_32),
REGDEF (xzr, 31, Z_64), REGDEF (XZR, 31, Z_64),
- /* Coprocessor register numbers. */
- REGSET (c, CN), REGSET (C, CN),
+ REGDEF (ip0, 16, R_64), REGDEF (IP0, 16, R_64),
+ REGDEF (ip1, 17, R_64), REGDEF (IP1, 17, R_64),
+ REGDEF (fp, 29, R_64), REGDEF (FP, 29, R_64),
+ REGDEF (lr, 30, R_64), REGDEF (LR, 30, R_64),
/* Floating-point single precision registers. */
REGSET (s, FP_S), REGSET (S, FP_S),
Note - despite the name this initialisation is not done when the frag
is created, but only when its type is assigned. A frag can be created
and used a long time before its type is set, so beware of assuming that
- this initialisationis performed first. */
+ this initialisation is performed first. */
#ifndef OBJ_ELF
void
case AARCH64_OPND_ADDR_SIMM7:
case AARCH64_OPND_ADDR_SIMM9:
case AARCH64_OPND_ADDR_SIMM9_2:
+ case AARCH64_OPND_ADDR_SIMM10:
case AARCH64_OPND_ADDR_UIMM12:
/* Immediate offset in an address. */
insn = get_aarch64_insn (buf);
case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC:
fixP->fx_r_type = (ilp32_p
? BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
- : BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC);
+ : BFD_RELOC_AARCH64_TLSDESC_LD64_LO12);
S_SET_THREAD_LOCAL (fixP->fx_addsy);
/* Should always be exported to object file, see
aarch64_force_relocation(). */
gas_assert (seg->use_rela_p);
break;
- case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC:
+ case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12:
case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21:
case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21:
case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC:
- case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC:
+ case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12:
case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19:
case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC:
case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21:
case BFD_RELOC_AARCH64_LDST32_LO12:
case BFD_RELOC_AARCH64_LDST64_LO12:
case BFD_RELOC_AARCH64_LDST8_LO12:
- case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC:
+ case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12:
case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21:
case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21:
case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC:
- case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC:
+ case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12:
case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19:
case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC:
case BFD_RELOC_AARCH64_TLSDESC_OFF_G1:
#ifdef OBJ_ELF
+/* Implement md_after_parse_args. This is the earliest time we need to decide
+ ABI. If no -mabi specified, the ABI will be decided by target triplet. */
+
+void
+aarch64_after_parse_args (void)
+{
+ if (aarch64_abi != AARCH64_ABI_NONE)
+ return;
+
+ /* DEFAULT_ARCH will have ":32" extension if it's configured for ILP32. */
+ if (strlen (default_arch) > 7 && strcmp (default_arch + 7, ":32") == 0)
+ aarch64_abi = AARCH64_ABI_ILP32;
+ else
+ aarch64_abi = AARCH64_ABI_LP64;
+}
+
const char *
elf64_aarch64_target_format (void)
{
AARCH64_FEATURE_CRC), "Cortex-A72"},
{"cortex-a73", AARCH64_FEATURE (AARCH64_ARCH_V8,
AARCH64_FEATURE_CRC), "Cortex-A73"},
+ {"cortex-a55", AARCH64_FEATURE (AARCH64_ARCH_V8_2,
+ AARCH64_FEATURE_RCPC | AARCH64_FEATURE_F16),
+ "Cortex-A55"},
+ {"cortex-a75", AARCH64_FEATURE (AARCH64_ARCH_V8_2,
+ AARCH64_FEATURE_RCPC | AARCH64_FEATURE_F16),
+ "Cortex-A75"},
{"exynos-m1", AARCH64_FEATURE (AARCH64_ARCH_V8,
AARCH64_FEATURE_CRC | AARCH64_FEATURE_CRYPTO),
"Samsung Exynos M1"},
+ {"falkor", AARCH64_FEATURE (AARCH64_ARCH_V8,
+ AARCH64_FEATURE_CRC | AARCH64_FEATURE_CRYPTO),
+ "Qualcomm Falkor"},
{"qdf24xx", AARCH64_FEATURE (AARCH64_ARCH_V8,
AARCH64_FEATURE_CRC | AARCH64_FEATURE_CRYPTO),
"Qualcomm QDF24XX"},
{"armv8-a", AARCH64_ARCH_V8},
{"armv8.1-a", AARCH64_ARCH_V8_1},
{"armv8.2-a", AARCH64_ARCH_V8_2},
+ {"armv8.3-a", AARCH64_ARCH_V8_3},
{NULL, AARCH64_ARCH_NONE}
};
{"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC, 0),
AARCH64_ARCH_NONE},
{"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO, 0),
- AARCH64_ARCH_NONE},
+ AARCH64_FEATURE (AARCH64_FEATURE_SIMD, 0)},
{"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP, 0),
AARCH64_ARCH_NONE},
{"lse", AARCH64_FEATURE (AARCH64_FEATURE_LSE, 0),
AARCH64_ARCH_NONE},
{"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD, 0),
- AARCH64_ARCH_NONE},
+ AARCH64_FEATURE (AARCH64_FEATURE_FP, 0)},
{"pan", AARCH64_FEATURE (AARCH64_FEATURE_PAN, 0),
AARCH64_ARCH_NONE},
{"lor", AARCH64_FEATURE (AARCH64_FEATURE_LOR, 0),
{"profile", AARCH64_FEATURE (AARCH64_FEATURE_PROFILE, 0),
AARCH64_ARCH_NONE},
{"sve", AARCH64_FEATURE (AARCH64_FEATURE_SVE, 0),
- AARCH64_FEATURE (AARCH64_FEATURE_FP
+ AARCH64_FEATURE (AARCH64_FEATURE_F16
+ | AARCH64_FEATURE_SIMD
+ | AARCH64_FEATURE_COMPNUM, 0)},
+ {"compnum", AARCH64_FEATURE (AARCH64_FEATURE_COMPNUM, 0),
+ AARCH64_FEATURE (AARCH64_FEATURE_F16
| AARCH64_FEATURE_SIMD, 0)},
+ {"rcpc", AARCH64_FEATURE (AARCH64_FEATURE_RCPC, 0),
+ AARCH64_ARCH_NONE},
+ {"dotprod", AARCH64_FEATURE (AARCH64_FEATURE_DOTPROD, 0),
+ AARCH64_ARCH_NONE},
{NULL, AARCH64_ARCH_NONE, AARCH64_ARCH_NONE},
};
projects / deliverable / binutils-gdb.git / blobdiff