struct arc_insn
{
- unsigned int insn;
+ unsigned long long int insn;
int nfixups;
struct arc_fixup fixups[MAX_INSN_FIXUPS];
long limm;
- bfd_boolean short_insn; /* Boolean value: TRUE if current insn is
- short. */
+ unsigned int len; /* Length of instruction in bytes. */
bfd_boolean has_limm; /* Boolean value: TRUE if limm field is
valid. */
bfd_boolean relax; /* Boolean value: TRUE if needs
(const struct arc_opcode *, const expressionS *, int,
const struct arc_flags *, int, struct arc_insn *);
-/* The cpu for which we are generating code. */
-static unsigned arc_target;
-static const char *arc_target_name;
-static unsigned arc_features;
+/* The selection of the machine type can come from different sources. This
+ enum is used to track how the selection was made in order to perform
+ error checks. */
+enum mach_selection_type
+ {
+ MACH_SELECTION_NONE,
+ MACH_SELECTION_FROM_DEFAULT,
+ MACH_SELECTION_FROM_CPU_DIRECTIVE,
+ MACH_SELECTION_FROM_COMMAND_LINE
+ };
-/* The default architecture. */
-static int arc_mach_type;
-
-/* TRUE if the cpu type has been explicitly specified. */
-static bfd_boolean mach_type_specified_p = FALSE;
+/* How the current machine type was selected. */
+static enum mach_selection_type mach_selection_mode = MACH_SELECTION_NONE;
/* The hash table of instruction opcodes. */
static struct hash_control *arc_opcode_hash;
{ 0, 0, 0, 0, 0 }
};
+/* Information about the cpu/variant we're assembling for. */
+static struct cpu_type selected_cpu = { 0, 0, 0, 0, 0 };
+
+/* A table with options. */
+static const struct feature_type
+{
+ unsigned feature;
+ unsigned cpus;
+ const char *name;
+}
+ feature_list[] =
+{
+ { ARC_CD, ARC_OPCODE_ARCV2, "code-density" },
+ { ARC_NPS400, ARC_OPCODE_ARC700, "nps400" },
+ { ARC_SPFP, ARC_OPCODE_ARCFPX, "single-precision FPX" },
+ { ARC_DPFP, ARC_OPCODE_ARCFPX, "double-precision FPX" },
+ { ARC_FPUDA, ARC_OPCODE_ARCv2EM, "double assist FP" }
+};
+
/* Used by the arc_reloc_op table. Order is important. */
#define O_gotoff O_md1 /* @gotoff relocation. */
#define O_gotpc O_md2 /* @gotpc relocation. */
const unsigned arc_num_relaxable_ins = ARRAY_SIZE (arc_relaxable_insns);
/* Flags to set in the elf header. */
-static flagword arc_eflag = 0x00;
+static const flagword arc_initial_eflag = 0x00;
/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
symbolS * GOT_symbol = 0;
}
-/* Like md_number_to_chars but used for limms. The 4-byte limm value,
- is encoded as 'middle-endian' for a little-endian target. FIXME!
- this function is used for regular 4 byte instructions as well. */
+/* Like md_number_to_chars but for middle-endian values. The 4-byte limm
+ value, is encoded as 'middle-endian' for a little-endian target. This
+ function is used for regular 4, 6, and 8 byte instructions as well. */
static void
-md_number_to_chars_midend (char *buf, valueT val, int n)
+md_number_to_chars_midend (char *buf, unsigned long long val, int n)
{
- if (n == 4)
+ switch (n)
{
+ case 2:
+ md_number_to_chars (buf, val, n);
+ break;
+ case 6:
+ md_number_to_chars (buf, (val & 0xffff00000000) >> 32, 2);
+ md_number_to_chars_midend (buf + 2, (val & 0xffffffff), 4);
+ break;
+ case 4:
md_number_to_chars (buf, (val & 0xffff0000) >> 16, 2);
md_number_to_chars (buf + 2, (val & 0xffff), 2);
+ break;
+ case 8:
+ md_number_to_chars_midend (buf, (val & 0xffffffff00000000) >> 32, 4);
+ md_number_to_chars_midend (buf + 4, (val & 0xffffffff), 4);
+ break;
+ default:
+ abort ();
}
- else
+}
+
+/* Check if a feature is allowed for a specific CPU. */
+
+static void
+arc_check_feature (void)
+{
+ unsigned i;
+
+ if (!selected_cpu.features
+ || !selected_cpu.name)
+ return;
+ for (i = 0; (i < ARRAY_SIZE (feature_list)); i++)
{
- md_number_to_chars (buf, val, n);
+ if ((selected_cpu.features & feature_list[i].feature)
+ && !(selected_cpu.flags & feature_list[i].cpus))
+ {
+ as_bad (_("invalid %s option for %s cpu"), feature_list[i].name,
+ selected_cpu.name);
+ }
}
}
/* Select an appropriate entry from CPU_TYPES based on ARG and initialise
- the relevant static global variables. */
+ the relevant static global variables. Parameter SEL describes where
+ this selection originated from. */
static void
-arc_select_cpu (const char *arg)
+arc_select_cpu (const char *arg, enum mach_selection_type sel)
{
int cpu_flags = 0;
int i;
+ /* We should only set a default if we've not made a selection from some
+ other source. */
+ gas_assert (sel != MACH_SELECTION_FROM_DEFAULT
+ || mach_selection_mode == MACH_SELECTION_NONE);
+
+ if ((mach_selection_mode == MACH_SELECTION_FROM_CPU_DIRECTIVE)
+ && (sel == MACH_SELECTION_FROM_CPU_DIRECTIVE))
+ as_bad (_("Multiple .cpu directives found"));
+
+ /* Look for a matching entry in CPU_TYPES array. */
for (i = 0; cpu_types[i].name; ++i)
{
if (!strcasecmp (cpu_types[i].name, arg))
{
- arc_target = cpu_types[i].flags;
- arc_target_name = cpu_types[i].name;
- arc_features = cpu_types[i].features;
- arc_mach_type = cpu_types[i].mach;
- cpu_flags = cpu_types[i].eflags;
+ /* If a previous selection was made on the command line, then we
+ allow later selections on the command line to override earlier
+ ones. However, a selection from a '.cpu NAME' directive must
+ match the command line selection, or we give a warning. */
+ if (mach_selection_mode == MACH_SELECTION_FROM_COMMAND_LINE)
+ {
+ gas_assert (sel == MACH_SELECTION_FROM_COMMAND_LINE
+ || sel == MACH_SELECTION_FROM_CPU_DIRECTIVE);
+ if (sel == MACH_SELECTION_FROM_CPU_DIRECTIVE
+ && selected_cpu.mach != cpu_types[i].mach)
+ {
+ as_warn (_("Command-line value overrides \".cpu\" directive"));
+ }
+ return;
+ }
+
+ /* Initialise static global data about selected machine type. */
+ selected_cpu.flags = cpu_types[i].flags;
+ selected_cpu.name = cpu_types[i].name;
+ selected_cpu.features |= cpu_types[i].features;
+ selected_cpu.mach = cpu_types[i].mach;
+ cpu_flags = cpu_types[i].eflags;
break;
}
}
if (!cpu_types[i].name)
as_fatal (_("unknown architecture: %s\n"), arg);
+
+ /* Check if set features are compatible with the chosen CPU. */
+ arc_check_feature ();
gas_assert (cpu_flags != 0);
- arc_eflag = (arc_eflag & ~EF_ARC_MACH_MSK) | cpu_flags;
+ selected_cpu.eflags = (arc_initial_eflag & ~EF_ARC_MACH_MSK) | cpu_flags;
+ mach_selection_mode = sel;
}
/* Here ends all the ARCompact extension instruction assembling
static void
arc_option (int ignore ATTRIBUTE_UNUSED)
{
- int mach = -1;
char c;
char *cpu;
+ const char *cpu_name;
c = get_symbol_name (&cpu);
- mach = arc_get_mach (cpu);
- if (mach == -1)
- goto bad_cpu;
+ if ((!strcmp ("ARC600", cpu))
+ || (!strcmp ("ARC601", cpu))
+ || (!strcmp ("A6", cpu)))
+ cpu_name = "arc600";
+ else if ((!strcmp ("ARC700", cpu))
+ || (!strcmp ("A7", cpu)))
+ cpu_name = "arc700";
+ else if (!strcmp ("EM", cpu))
+ cpu_name = "arcem";
+ else if (!strcmp ("HS", cpu))
+ cpu_name = "archs";
+ else if (!strcmp ("NPS400", cpu))
+ cpu_name = "nps400";
+ else
+ cpu_name = NULL;
- if (!mach_type_specified_p)
- {
- if ((!strcmp ("ARC600", cpu))
- || (!strcmp ("ARC601", cpu))
- || (!strcmp ("A6", cpu)))
- {
- md_parse_option (OPTION_MCPU, "arc600");
- }
- else if ((!strcmp ("ARC700", cpu))
- || (!strcmp ("A7", cpu)))
- {
- md_parse_option (OPTION_MCPU, "arc700");
- }
- else if (!strcmp ("EM", cpu))
- {
- md_parse_option (OPTION_MCPU, "arcem");
- }
- else if (!strcmp ("HS", cpu))
- {
- md_parse_option (OPTION_MCPU, "archs");
- }
- else if (!strcmp ("NPS400", cpu))
- {
- md_parse_option (OPTION_MCPU, "nps400");
- }
- else
- as_fatal (_("could not find the architecture"));
+ if (cpu_name != NULL)
+ arc_select_cpu (cpu_name, MACH_SELECTION_FROM_CPU_DIRECTIVE);
+ else
+ as_fatal (_("invalid architecture `%s' in .cpu directive"), cpu);
- if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, mach))
- as_fatal (_("could not set architecture and machine"));
+ if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, selected_cpu.mach))
+ as_fatal (_("could not set architecture and machine"));
- /* Set elf header flags. */
- bfd_set_private_flags (stdoutput, arc_eflag);
- }
- else
- if (arc_mach_type != mach)
- as_warn (_("Command-line value overrides \".cpu\" directive"));
+ /* Set elf header flags. */
+ bfd_set_private_flags (stdoutput, selected_cpu.eflags);
restore_line_pointer (c);
demand_empty_rest_of_line ();
- return;
-
- bad_cpu:
- restore_line_pointer (c);
- as_bad (_("invalid identifier for \".cpu\""));
- ignore_rest_of_line ();
}
/* Smartly print an expression. */
/* FIXME! the reloc size is wrong in the BFD file.
When it is fixed please delete me. */
- size = (insn->short_insn && !fixup->islong) ? 2 : 4;
+ size = ((insn->len == 2) && !fixup->islong) ? 2 : 4;
if (fixup->islong)
- offset = (insn->short_insn) ? 2 : 4;
+ offset = insn->len;
/* Some fixups are only used internally, thus no howto. */
if ((int) fixup->reloc == 0)
{
/* FIXME! the reloc size is wrong in the BFD file.
When it is fixed please enable me.
- size = (insn->short_insn && !fixup->islong) ? 2 : 4; */
+ size = ((insn->len == 2 && !fixup->islong) ? 2 : 4; */
pcrel = fixup->pcrel;
}
else
emit_insn0 (struct arc_insn *insn, char *where, bfd_boolean relax)
{
char *f = where;
+ size_t total_len;
- pr_debug ("Emit insn : 0x%x\n", insn->insn);
- pr_debug ("\tShort : 0x%d\n", insn->short_insn);
+ pr_debug ("Emit insn : 0x%llx\n", insn->insn);
+ pr_debug ("\tLength : 0x%d\n", insn->len);
pr_debug ("\tLong imm: 0x%lx\n", insn->limm);
/* Write out the instruction. */
- if (insn->short_insn)
- {
- if (insn->has_limm)
- {
- if (!relax)
- f = frag_more (6);
- md_number_to_chars (f, insn->insn, 2);
- md_number_to_chars_midend (f + 2, insn->limm, 4);
- dwarf2_emit_insn (6);
- }
- else
- {
- if (!relax)
- f = frag_more (2);
- md_number_to_chars (f, insn->insn, 2);
- dwarf2_emit_insn (2);
- }
- }
- else
- {
- if (insn->has_limm)
- {
- if (!relax)
- f = frag_more (8);
- md_number_to_chars_midend (f, insn->insn, 4);
- md_number_to_chars_midend (f + 4, insn->limm, 4);
- dwarf2_emit_insn (8);
- }
- else
- {
- if (!relax)
- f = frag_more (4);
- md_number_to_chars_midend (f, insn->insn, 4);
- dwarf2_emit_insn (4);
- }
- }
+ total_len = insn->len + (insn->has_limm ? 4 : 0);
+ if (!relax)
+ f = frag_more (total_len);
+
+ md_number_to_chars_midend(f, insn->insn, insn->len);
+
+ if (insn->has_limm)
+ md_number_to_chars_midend (f + insn->len, insn->limm, 4);
+ dwarf2_emit_insn (total_len);
if (!relax)
apply_fixups (insn, frag_now, (f - frag_now->fr_literal));
static bfd_boolean
check_cpu_feature (insn_subclass_t sc)
{
- if (is_code_density_p (sc) && !(arc_features & ARC_CD))
+ if (is_code_density_p (sc) && !(selected_cpu.features & ARC_CD))
return FALSE;
- if (is_spfp_p (sc) && !(arc_features & ARC_SPFP))
+ if (is_spfp_p (sc) && !(selected_cpu.features & ARC_SPFP))
return FALSE;
- if (is_dpfp_p (sc) && !(arc_features & ARC_DPFP))
+ if (is_dpfp_p (sc) && !(selected_cpu.features & ARC_DPFP))
return FALSE;
- if (is_fpuda_p (sc) && !(arc_features & ARC_FPUDA))
+ if (is_fpuda_p (sc) && !(selected_cpu.features & ARC_FPUDA))
return FALSE;
- if (is_nps400_p (sc) && !(arc_features & ARC_NPS400))
+ if (is_nps400_p (sc) && !(selected_cpu.features & ARC_NPS400))
return FALSE;
return TRUE;
int tokidx = 0;
const expressionS *t = &emptyE;
- pr_debug ("%s:%d: find_opcode_match: trying opcode 0x%08X ",
+ pr_debug ("%s:%d: find_opcode_match: trying opcode 0x%08llX ",
frag_now->fr_file, frag_now->fr_line, opcode->opcode);
/* Don't match opcodes that don't exist on this
architecture. */
- if (!(opcode->cpu & arc_target))
+ if (!(opcode->cpu & selected_cpu.flags))
goto match_failed;
if (!check_cpu_feature (opcode->subclass))
switch (operand->flags & ARC_OPERAND_TYPECHECK_MASK)
{
case ARC_OPERAND_ADDRTYPE:
- /* Check to be an address type. */
- if (tok[tokidx].X_op != O_addrtype)
- goto match_failed;
+ {
+ const char *errmsg = NULL;
+
+ /* Check to be an address type. */
+ if (tok[tokidx].X_op != O_addrtype)
+ goto match_failed;
+
+ /* All address type operands need to have an insert
+ method in order to check that we have the correct
+ address type. */
+ gas_assert (operand->insert != NULL);
+ (*operand->insert) (0, tok[tokidx].X_add_number,
+ &errmsg);
+ if (errmsg != NULL)
+ goto match_failed;
+ }
break;
case ARC_OPERAND_IR:
if (tok[tokidx].X_op != O_constant)
goto de_fault;
}
- /* Fall-through */
+ /* Fall through. */
case O_constant:
/* Check the range. */
if (operand->bits != 32
goto match_failed;
break;
}
+ /* Fall through. */
default:
de_fault:
if (operand->default_reloc == 0)
case O_tlsie:
if (!(operand->flags & ARC_OPERAND_LIMM))
goto match_failed;
+ /* Fall through. */
case O_absent:
if (!generic_reloc_p (operand->default_reloc))
goto match_failed;
return NULL;
}
-/* The long instructions are not stored in a hash (there's not many of
- them) and so there's no arc_opcode_hash_entry structure to return. This
- helper function for find_special_case_long_opcode takes an arc_opcode
- result and places it into a fake arc_opcode_hash_entry that points to
- the single arc_opcode OPCODE, which is then returned. */
-
-static const struct arc_opcode_hash_entry *
-build_fake_opcode_hash_entry (const struct arc_opcode *opcode)
-{
- static struct arc_opcode_hash_entry entry;
- static struct arc_opcode tmp[2];
- static const struct arc_opcode *ptr[2];
-
- memcpy (&tmp[0], opcode, sizeof (struct arc_opcode));
- memset (&tmp[1], 0, sizeof (struct arc_opcode));
- entry.count = 1;
- entry.opcode = ptr;
- ptr[0] = tmp;
- ptr[1] = NULL;
- return &entry;
-}
-
-
-/* Used by the assembler to match the list of tokens against a long (48 or
- 64 bits) instruction. If a matching long instruction is found, then
- some of the tokens are consumed in this function and converted into a
- single LIMM value, which is then added to the end of the token list,
- where it will be consumed by a LIMM operand that exists in the base
- opcode of the long instruction. */
-
-static const struct arc_opcode_hash_entry *
-find_special_case_long_opcode (const char *opname,
- int *ntok ATTRIBUTE_UNUSED,
- expressionS *tok ATTRIBUTE_UNUSED,
- int *nflgs,
- struct arc_flags *pflags)
-{
- unsigned i;
-
- if (*ntok == MAX_INSN_ARGS)
- return NULL;
-
- for (i = 0; i < arc_num_long_opcodes; ++i)
- {
- struct arc_opcode fake_opcode;
- const struct arc_opcode *opcode;
- struct arc_insn insn;
- expressionS *limm_token;
-
- opcode = &arc_long_opcodes[i].base_opcode;
-
- if (!(opcode->cpu & arc_target))
- continue;
-
- if (!check_cpu_feature (opcode->subclass))
- continue;
-
- if (strcmp (opname, opcode->name) != 0)
- continue;
-
- /* Check that the flags are a match. */
- if (!parse_opcode_flags (opcode, *nflgs, pflags))
- continue;
-
- /* Parse the LIMM operands into the LIMM template. */
- memset (&fake_opcode, 0, sizeof (fake_opcode));
- fake_opcode.name = "fake limm";
- fake_opcode.opcode = arc_long_opcodes[i].limm_template;
- fake_opcode.mask = arc_long_opcodes[i].limm_mask;
- fake_opcode.cpu = opcode->cpu;
- fake_opcode.insn_class = opcode->insn_class;
- fake_opcode.subclass = opcode->subclass;
- memcpy (&fake_opcode.operands[0],
- &arc_long_opcodes[i].operands,
- MAX_INSN_ARGS);
- /* Leave fake_opcode.flags as zero. */
-
- pr_debug ("Calling assemble_insn to build fake limm value\n");
- assemble_insn (&fake_opcode, tok, *ntok,
- NULL, 0, &insn);
- pr_debug (" got limm value: 0x%x\n", insn.insn);
-
- /* Now create a new token at the end of the token array (We know this
- is safe as the token array is always created with enough space for
- MAX_INSN_ARGS, and we check at the start at the start of this
- function that we're not there yet). This new token will
- correspond to a LIMM operand that will be contained in the
- base_opcode of the arc_long_opcode. */
- limm_token = &tok[(*ntok)];
- (*ntok)++;
-
- /* Modify the LIMM token to hold the constant. */
- limm_token->X_op = O_constant;
- limm_token->X_add_number = insn.insn;
-
- /* Return the base opcode. */
- return build_fake_opcode_hash_entry (opcode);
- }
-
- return NULL;
-}
-
/* Used to find special case opcode. */
static const struct arc_opcode_hash_entry *
if (entry == NULL)
entry = find_special_case_flag (opname, nflgs, pflags);
- if (entry == NULL)
- entry = find_special_case_long_opcode (opname, ntok, tok, nflgs, pflags);
-
return entry;
}
as_bad (_("inappropriate arguments for opcode '%s'"), opname);
else
as_bad (_("opcode '%s' not supported for target %s"), opname,
- arc_target_name);
+ selected_cpu.name);
}
else
as_bad (_("unknown opcode '%s'"), opname);
{
const struct arc_opcode *opcode = arc_opcodes;
- if (!mach_type_specified_p)
- arc_select_cpu (TARGET_WITH_CPU);
+ if (mach_selection_mode == MACH_SELECTION_NONE)
+ arc_select_cpu (TARGET_WITH_CPU, MACH_SELECTION_FROM_DEFAULT);
/* The endianness can be chosen "at the factory". */
target_big_endian = byte_order == BIG_ENDIAN;
- if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, arc_mach_type))
+ if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, selected_cpu.mach))
as_warn (_("could not set architecture and machine"));
/* Set elf header flags. */
- bfd_set_private_flags (stdoutput, arc_eflag);
+ bfd_set_private_flags (stdoutput, selected_cpu.eflags);
/* Set up a hash table for the instructions. */
arc_opcode_hash = hash_new ();
{
const char *retval;
- if (!(auxr->cpu & arc_target))
+ if (!(auxr->cpu & selected_cpu.flags))
continue;
if ((auxr->subclass != NONE)
/* Insert an operand value into an instruction. */
-static unsigned
-insert_operand (unsigned insn,
+static unsigned long long
+insert_operand (unsigned long long insn,
const struct arc_operand *operand,
- offsetT val,
+ long long val,
const char *file,
unsigned line)
{
val, min, max, file, line);
}
- pr_debug ("insert field: %ld <= %ld <= %ld in 0x%08x\n",
+ pr_debug ("insert field: %ld <= %ld <= %ld in 0x%08llx\n",
min, val, max, insn);
if ((operand->flags & ARC_OPERAND_ALIGNED32)
case BFD_RELOC_ARC_TLS_LE_32:
gas_assert (!fixP->fx_addsy);
gas_assert (!fixP->fx_subsy);
+ /* Fall through. */
case BFD_RELOC_ARC_GOTOFF:
case BFD_RELOC_ARC_32_ME:
case BFD_RELOC_ARC_S21W_PCREL_PLT:
reloc = BFD_RELOC_ARC_S21W_PCREL;
+ /* Fall through. */
case BFD_RELOC_ARC_S25W_PCREL:
case BFD_RELOC_ARC_S21W_PCREL:
apply_fixups (&insn, fragP, fix);
- size = insn.short_insn ? (insn.has_limm ? 6 : 2) : (insn.has_limm ? 8 : 4);
+ size = insn.len + (insn.has_limm ? 4 : 0);
gas_assert (table_entry->rlx_length == size);
emit_insn0 (&insn, dest, TRUE);
if (!assembling_insn)
return FALSE;
- /* Handle only registers and address types. */
- if (e->X_op != O_absent)
+ if (e->X_op == O_symbol)
return FALSE;
sym = hash_find (arc_reg_hash, name);
case OPTION_MCPU:
{
- arc_select_cpu (arg);
- mach_type_specified_p = TRUE;
+ arc_select_cpu (arg, MACH_SELECTION_FROM_COMMAND_LINE);
break;
}
break;
case OPTION_CD:
- /* This option has an effect only on ARC EM. */
- if (arc_target & ARC_OPCODE_ARCv2EM)
- arc_features |= ARC_CD;
- else
- as_warn (_("Code density option invalid for selected CPU"));
+ selected_cpu.features |= ARC_CD;
+ arc_check_feature ();
break;
case OPTION_RELAX:
break;
case OPTION_NPS400:
- arc_features |= ARC_NPS400;
+ selected_cpu.features |= ARC_NPS400;
+ arc_check_feature ();
break;
case OPTION_SPFP:
- arc_features |= ARC_SPFP;
+ selected_cpu.features |= ARC_SPFP;
+ arc_check_feature ();
break;
case OPTION_DPFP:
- arc_features |= ARC_DPFP;
+ selected_cpu.features |= ARC_DPFP;
+ arc_check_feature ();
break;
case OPTION_FPUDA:
- /* This option has an effect only on ARC EM. */
- if (arc_target & ARC_OPCODE_ARCv2EM)
- arc_features |= ARC_FPUDA;
- else
- as_warn (_("FPUDA invalid for selected CPU"));
+ selected_cpu.features |= ARC_FPUDA;
+ arc_check_feature ();
break;
/* Dummy options are accepted but have no effect. */
struct arc_insn *insn)
{
const expressionS *reloc_exp = NULL;
- unsigned image;
+ unsigned long long image;
const unsigned char *argidx;
int i;
int tokidx = 0;
memset (insn, 0, sizeof (*insn));
image = opcode->opcode;
- pr_debug ("%s:%d: assemble_insn: %s using opcode %x\n",
+ pr_debug ("%s:%d: assemble_insn: %s using opcode %llx\n",
frag_now->fr_file, frag_now->fr_line, opcode->name,
opcode->opcode);
image = insert_operand (image, operand, regs, NULL, 0);
break;
}
+ /* Fall through. */
default:
/* This operand needs a relocation. */
break;
case O_pcl:
reloc = ARC_RELOC_TABLE (t->X_md)->reloc;
- if (ARC_SHORT (opcode->mask) || opcode->insn_class == JUMP)
+ if (arc_opcode_len (opcode) == 2
+ || opcode->insn_class == JUMP)
as_bad_where (frag_now->fr_file, frag_now->fr_line,
_("Unable to use @pcl relocation for insn %s"),
opcode->name);
insn->relax = relax_insn_p (opcode, tok, ntok, pflags, nflg);
- /* Short instruction? */
- insn->short_insn = ARC_SHORT (opcode->mask) ? TRUE : FALSE;
+ /* Instruction length. */
+ insn->len = arc_opcode_len (opcode);
insn->insn = image;
static void
check_zol (symbolS *s)
{
- switch (arc_mach_type)
+ switch (selected_cpu.mach)
{
case bfd_mach_arc_arcv2:
- if (arc_target & ARC_OPCODE_ARCv2EM)
+ if (selected_cpu.flags & ARC_OPCODE_ARCv2EM)
return;
if (is_br_jmp_insn_p (arc_last_insns[0].opcode)
/* Check the opcode ranges. */
moplow = 0x05;
- mophigh = (arc_target & (ARC_OPCODE_ARCv2EM
- | ARC_OPCODE_ARCv2HS)) ? 0x07 : 0x0a;
+ mophigh = (selected_cpu.flags & (ARC_OPCODE_ARCv2EM
+ | ARC_OPCODE_ARCv2HS)) ? 0x07 : 0x0a;
if ((einsn.major > mophigh) || (einsn.major < moplow))
as_fatal (_("major opcode not in range [0x%02x - 0x%02x]"), moplow, mophigh);
break;
}
- arc_ext_opcodes = arcExtMap_genOpcode (&einsn, arc_target, &errmsg);
+ arc_ext_opcodes = arcExtMap_genOpcode (&einsn, selected_cpu.flags, &errmsg);
if (arc_ext_opcodes == NULL)
{
if (errmsg)
/* Auxiliary register. */
auxr = XNEW (struct arc_aux_reg);
auxr->name = ereg.name;
- auxr->cpu = arc_target;
+ auxr->cpu = selected_cpu.flags;
auxr->subclass = NONE;
auxr->address = ereg.number;
retval = hash_insert (arc_aux_hash, auxr->name, (void *) auxr);
projects / deliverable / binutils-gdb.git / blobdiff